 | 2009 |
|---|
| 12 |       | Terrence S. T. Mak,
Peter Y. K. Cheung,
Wayne Luk,
Kai-Pui Lam:
A DP-network for optimal dynamic routing in network-on-chip.
CODES+ISSS 2009: 119-128 |
| 2008 |
|---|
| 11 | | Terrence S. T. Mak,
N. Pete Sedcole,
Peter Y. K. Cheung,
Wayne Luk:
High-throughput interconnect wave-pipelining for global communication in FPGAs.
FPGA 2008: 258 |
| 10 | | Terrence S. T. Mak,
Crescenzo D'Alessandro,
N. Pete Sedcole,
Peter Y. K. Cheung,
Alexandre Yakovlev,
Wayne Luk:
Implementation of Wave-Pipelined Interconnects in FPGAs.
NOCS 2008: 213-214 |
| 9 | | Terrence S. T. Mak,
N. Pete Sedcole,
Peter Y. K. Cheung,
Wayne Luk:
Interconnection lengths and delays estimation for communication links in FPGAs.
SLIP 2008: 1-10 |
| 8 | | Terrence S. T. Mak,
Crescenzo D'Alessandro,
N. Pete Sedcole,
Peter Y. K. Cheung,
Alexandre Yakovlev,
Wayne Luk:
Global interconnections in FPGAs: modeling and performance analysis.
SLIP 2008: 51-58 |
| 2007 |
|---|
| 7 | | Terrence S. T. Mak,
Kai-Pui Lam,
H. S. Ng,
G. Rachmuth,
C.-S. Poon:
A Current-Mode Analog Circuit for Reinforcement Learning Problems.
ISCAS 2007: 1301-1304 |
| 6 | | Terrence S. T. Mak,
N. Pete Sedcole,
Peter Y. K. Cheung,
Wayne Luk,
Kai-Pui Lam:
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing.
NOCS 2007: 173-182 |
| 2006 |
|---|
| 5 | | Terrence S. T. Mak,
N. Pete Sedcole,
Peter Y. K. Cheung,
Wayne Luk:
On-FPGA Communication Architectures and Design Factors.
FPL 2006: 1-8 |
| 2004 |
|---|
| 4 | | Terrence S. T. Mak,
Kai-Pui Lam:
Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA.
CSB 2004: 512-514 |
| 3 | | Terrence S. T. Mak,
Kai-Pui Lam:
FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation.
FPL 2004: 1076-1079 |
| 2 | | Terrence S. T. Mak,
Kai-Pui Lam:
On Computing Maximum Likelihood Phylogeny Using FPGA p.
FPL 2004: 1188 |
| 2003 |
|---|
| 1 | | Terrence S. T. Mak,
Kai-Pui Lam:
High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign.
CSB 2003: 470-473 |
