 | 2008 |
|---|
| 11 |       | Mohammad M. Mansour:
Parallel channel interleavers for 3GPP2/UMB.
SiPS 2008: 55-60 |
| 2005 |
|---|
| 10 | | Mohammad M. Mansour,
Naresh R. Shanbhag:
A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes.
VLSI Signal Processing 40(3): 371-382 (2005) |
| 2004 |
|---|
| 9 | | Makram M. Mansour,
Mohammad M. Mansour,
Amit Mehrotra:
Analysis of MOS cross-coupled LC-tank oscillators using short-channel device equations.
ASP-DAC 2004: 181-185 |
| 2003 |
|---|
| 8 | | Mohammad M. Mansour,
Naresh R. Shanbhag:
Architecture-aware low-density parity-check codes.
ISCAS (2) 2003: 57-60 |
| 7 | | Mohammad M. Mansour,
Amit Mehrotra:
Efficient core designs based on parameterized macrocells with accurate delay models.
ISCAS (5) 2003: 517-520 |
| 6 | | Makram M. Mansour,
Mohammad M. Mansour,
Amit Mehrotra:
Parameterized Macrocells with Accurate Delay Models for Core-Based Designs.
ISQED 2003: 319- |
| 5 | | Makram M. Mansour,
Mohammad M. Mansour,
Amit Mehrotra:
Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit Design.
ISVLSI 2003: 62-69 |
| 4 | | Mohammad M. Mansour,
Naresh R. Shanbhag:
VLSI architectures for SISO-APP decoders.
IEEE Trans. VLSI Syst. 11(4): 627-650 (2003) |
| 3 | | Mohammad M. Mansour,
Naresh R. Shanbhag:
High-throughput LDPC decoders.
IEEE Trans. VLSI Syst. 11(6): 976-996 (2003) |
| 2002 |
|---|
| 2 | | Mohammad M. Mansour,
Naresh R. Shanbhag:
Simplified current and delay models for deep submicron CMOS digital circuits.
ISCAS (5) 2002: 109-112 |
| 1 | | Mohammad M. Mansour,
Naresh R. Shanbhag:
Low-power VLSI decoder architectures for LDPC codes.
ISLPED 2002: 284-289 |
