Nazanin Mansouri

	2008
18		Youngsik Kim, Nazanin Mansouri: Automated formal verification of scheduling with speculative code motions. ACM Great Lakes Symposium on VLSI 2008: 95-100
17		Deniz Dal, Nazanin Mansouri: Determining the Optimal Number of Islands in Power Islands Synthesis. ISVLSI 2008: 22-27
	2007
16		Deniz Dal, Nazanin Mansouri: A high-level register optimization technique for minimizing leakage and dynamic power. ACM Great Lakes Symposium on VLSI 2007: 517-520
15		Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie: Reliability-Centric High-Level Synthesis CoRR abs/0710.4684: (2007)
	2006
14		Shweta Shah, Nazanin Mansouri, Adrián Núñez-Aldana: Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits. CONIELECOMP 2006: 38
13		Suleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Ozcan Ozturk: An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors. ISCIS 2006: 267-276
12		Deniz Dal, Adrian Nunez, Nazanin Mansouri: Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron. ISQED 2006: 165-170
	2005
11		Youngsik Kim, Parija Sule, Nazanin Mansouri: Exploiting PSL standard assertions in a theorem-proving-based verification environment. ACM Great Lakes Symposium on VLSI 2005: 400-403
10		Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie: Reliability-Centric High-Level Synthesis. DATE 2005: 1258-1263
9		Suleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung: An ILP Formulation for Reliability-Oriented High-Level Synthesis. ISQED 2005: 364-369
8		Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung: Reliability-Centric Hardware/Software Co-Design. ISQED 2005: 375-380
	2004
7		Anli He, Parija Sule, Youngsik Kim, Nazanin Mansouri: Exploiting OVL standard assertions in a theorem-proving-based verification environment. Circuits, Signals, and Systems 2004: 249-254
6		Shekhar Kopuri, Nazanin Mansouri: Enhancing scheduling solutions through ant colony optimization. ISCAS (5) 2004: 257-260
5		Youngsik Kim, Shekhar Kopuri, Nazanin Mansouri: Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD). ISQED 2004: 110-115
	2003
4		Suleyman Tosun, Hakduran Koc, Nazanin Mansouri: Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs. VLSI 2003: 382-
	2000
3		Nazanin Mansouri, Ranga Vemuri: Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs. Formal Methods in System Design 16(1): 59-91 (2000)
	1999
2		Nazanin Mansouri, Ranga Vemuri: Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. DATE 1999: 223-
	1998
1		Nazanin Mansouri, Ranga Vemuri: A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool. FMCAD 1998: 204-221

Coauthor Index

1	Ercument Arvas	[8] [9] [10] [15]
2	Deniz Dal	[12] [16] [17]
3	Anli He	[7]
4	Wei-Lun Hung	[8] [9]
5	Mahmut T. Kandemir	[8] [9] [10] [13] [15]
6	Youngsik Kim	[5] [7] [11] [18]
7	Hakduran Koc	[4]
8	Shekhar Kopuri	[5] [6]
9	Adrian Nunez	[12]
10	Adrián Núñez-Aldana	[14]
11	Ozcan Ozturk	[9] [13]
12	Shweta Shah	[14]
13	Parija Sule	[7] [11]
14	Suleyman Tosun	[4] [8] [9] [10] [13] [15]
15	Ranga Vemuri	[1] [2] [3]
16	Yuan Xie	[8] [9] [10] [15]

Colors in the list of coauthors