 | 2009 |
|---|
| 54 |       | Erik Jan Marinissen,
Dae Young Lee,
John P. Hayes,
Chris Sellathamby,
Brian Moore,
Steven Slupsky,
Laurence Pujol:
Contactless testing: Possibility or pipe-dream?
DATE 2009: 676-681 |
| 53 | | Erik Jan Marinissen,
Yervant Zorian:
Guest Editors' Introduction: The Status of IEEE Std 1500.
IEEE Design & Test of Computers 26(1): 6-7 (2009) |
| 52 | | Erik Jan Marinissen,
Yervant Zorian:
IEEE Std 1500 Enables Modular SoC Testing.
IEEE Design & Test of Computers 26(1): 8-17 (2009) |
| 51 | | Sandeep Kumar Goel,
Erik Jan Marinissen,
Anuja Sehgal,
Krishnendu Chakrabarty:
Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling.
IEEE Trans. Computers 58(3): 409-423 (2009) |
| 2008 |
|---|
| 50 | | Ozgur Sinanoglu,
Erik Jan Marinissen:
Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing.
DATE 2008: 182-187 |
| 49 | | Rob Aitken,
Erik Jan Marinissen:
Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis.
IEEE Design & Test of Computers 25(3): 206-207 (2008) |
| 48 | | Erik Jan Marinissen:
Bugs, moths, grasshoppers, and whales.
IEEE Design & Test of Computers 25(3): 288 (2008) |
| 2007 |
|---|
| 47 | | Paul Wielage,
Erik Jan Marinissen,
Michel Altheimer,
Clemens Wouters:
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO.
DATE 2007: 853-858 |
| 46 | | Tobias Dubois,
Erik Jan Marinissen,
Mohamed Azimane,
Paul Wielage,
Erik Larsson,
Clemens Wouters:
Test quality analysis and improvement for an embedded asynchronous FIFO.
DATE 2007: 859-864 |
| 45 | | Sandeep Kumar Goel,
Erik Jan Marinissen:
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
CoRR abs/0710.4687: (2007) |
| 44 | | Erik Jan Marinissen,
Axel Jantsch,
Nicola Nicolici:
DATE 07 workshop on diagnostic services in NoCs.
IEEE Design & Test of Computers 24(5): 510 (2007) |
| 2006 |
|---|
| 43 | | Anuja Sehgal,
Sandeep Kumar Goel,
Erik Jan Marinissen,
Krishnendu Chakrabarty:
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips.
DATE 2006: 285-290 |
| 42 | | Alexandre M. Amory,
Kees Goossens,
Erik Jan Marinissen,
Marcelo Lubaszewski,
Fernando Moraes:
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.
European Test Symposium 2006: 213-218 |
| 41 | | Mitra Subhasish,
Ondrej Novák,
Hana Kubatova,
Bashir M. Al-Hashimi,
Erik Jan Marinissen,
C. P. Ravikumar:
Conference Reports.
IEEE Design & Test of Computers 23(4): 262-265 (2006) |
| 2005 |
|---|
| 40 | | Tom Waayers,
Erik Jan Marinissen,
Maurice Lousberg:
IEEE Std 1500 Compliant Infrastructure forModular SOC Testing.
Asian Test Symposium 2005: 450 |
| 39 | | Sandeep Kumar Goel,
Erik Jan Marinissen:
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips.
DATE 2005: 44-49 |
| 38 | | Erik Jan Marinissen,
Betty Prince,
Doris Keitel-Schulz,
Yervant Zorian:
Challenges in Embedded Memory Design and Test.
DATE 2005: 722-727 |
| 37 | | Henk D. L. Hollmann,
Erik Jan Marinissen,
Bart Vermeulen:
Optimal Interconnect ATPG Under a Ground-Bounce Constraint.
J. Electronic Testing 21(1): 17-31 (2005) |
| 2004 |
|---|
| 36 | | Sandeep Kumar Goel,
Kuoshu Chiu,
Erik Jan Marinissen,
Toan Nguyen,
Steven Oostdijk:
Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip.
DATE 2004: 108-113 |
| 35 | | Anuja Sehgal,
Sandeep Kumar Goel,
Erik Jan Marinissen,
Krishnendu Chakrabarty:
IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores.
ITC 2004: 1203-1212 |
| 34 | | Erik Jan Marinissen:
Security vs. Test Quality: Can We Really Only Have One at a Time?
ITC 2004: 1411 |
| 33 | | Bart Vermeulen,
Camelia Hora,
Bram Kruseman,
Erik Jan Marinissen,
Robert Van Rijsinge:
Trends in Testing Integrated Circuits.
ITC 2004: 688-697 |
| 2003 |
|---|
| 32 | | Erik Jan Marinissen,
Bart Vermeulen,
Robert Madge,
Michael Kessler,
Michael Müller:
Creating Value Through Test.
DATE 2003: 10402-10409 |
| 31 | | Sandeep Kumar Goel,
Erik Jan Marinissen:
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization.
DATE 2003: 10738-10741 |
| 30 | | Henk D. L. Hollmann,
Erik Jan Marinissen,
Bart Vermeulen:
Optimal Interconnect ATPG Under a Ground-Bounce Constraint.
ITC 2003: 369-378 |
| 29 | | Sandeep Kumar Goel,
Erik Jan Marinissen:
SOC test architecture design for efficient utilization of test bandwidth.
ACM Trans. Design Autom. Electr. Syst. 8(4): 399-429 (2003) |
| 28 | | Erik Jan Marinissen,
Bart Vermeulen,
Henk D. L. Hollmann,
Ben Bennetts:
Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint.
IEEE Design & Test of Computers 20(2): 8-18 (2003) |
| 27 | | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip.
IEEE Trans. Computers 52(12): 1619-1632 (2003) |
| 26 | | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
Efficient test access mechanism optimization for system-on-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 635-643 (2003) |
| 25 | | Sandeep Kumar Goel,
Erik Jan Marinissen:
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips.
J. Electronic Testing 19(4): 425-435 (2003) |
| 2002 |
|---|
| 24 | | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
Recent Advances in Test Planning for Modular Testing of Core-Based SOCs.
Asian Test Symposium 2002: 320- |
| 23 | | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs.
DAC 2002: 685-690 |
| 22 | | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
Efficient Wrapper/TAM Co-Optimization for Large SOCs.
DATE 2002: 491-498 |
| 21 | | Vikram Iyengar,
Sandeep Kumar Goel,
Erik Jan Marinissen,
Krishnendu Chakrabarty:
Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints.
ITC 2002: 1159-1168 |
| 20 | | Erik Jan Marinissen,
Vikram Iyengar,
Krishnendu Chakrabarty:
A Set of Benchmarks fo Modular Testing of SOCs.
ITC 2002: 519-528 |
| 19 | | Sandeep Kumar Goel,
Erik Jan Marinissen:
Effective and Efficient Test Architecture Design for SOCs.
ITC 2002: 529-538 |
| 18 | | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization.
VTS 2002: 253-258 |
| 17 | | Sandeep Kumar Goel,
Erik Jan Marinissen:
Cluster-Based Test Architecture Design for System-on-Chip.
VTS 2002: 259-264 |
| 16 |  | Krishnendu Chakrabarty,
Erik Jan Marinissen:
How Useful are the ITC 02 SoC Test Benchmarks?
IEEE Design & Test of Computers 19(5): 120, 119 (2002) |
| 15 | | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip.
J. Electronic Testing 18(2): 213-230 (2002) |
| 14 | | Erik Jan Marinissen,
Rohit Kapur,
Maurice Lousberg,
Teresa L. McLaurin,
Mike Ricchetti,
Yervant Zorian:
On IEEE P1500's Standard for Embedded Core Test.
J. Electronic Testing 18(4-5): 365-383 (2002) |
| 13 | | Erik Jan Marinissen:
The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs.
J. Electronic Testing 18(4-5): 435-454 (2002) |
| 2001 |
|---|
| 12 | | Vikram Iyengar,
Krishnendu Chakrabarty,
Erik Jan Marinissen:
Test wrapper and test access mechanism co-optimization for system-on-chip.
ITC 2001: 1023-1032 |
| 11 | | Erik Jan Marinissen:
An Industrial Approach to Core-Based System Chip Testing.
VLSI-SOC 2001: 389-400 |
| 10 | | Gundolf Kiefer,
Harald P. E. Vranken,
Erik Jan Marinissen,
Hans-Joachim Wunderlich:
Application of Deterministic Logic BIST on Industrial Circuits.
J. Electronic Testing 17(3-4): 351-362 (2001) |
| 2000 |
|---|
| 9 | | Yervant Zorian,
Erik Jan Marinissen:
System chip test: how will it impact your design?
DAC 2000: 136-141 |
| 8 | | Gundolf Kiefer,
Hans-Joachim Wunderlich,
Harald P. E. Vranken,
Erik Jan Marinissen:
Application of deterministic logic BIST on industrial circuits.
ITC 2000: 105-114 |
| 7 | | Yervant Zorian,
Erik Jan Marinissen,
Rohit Kapur:
On using IEEE P1500 SECT for test plug-n-play.
ITC 2000: 770-777 |
| 6 | | Yervant Zorian,
Erik Jan Marinissen,
Maurice Lousberg,
Sandeep Kumar Goel:
Wrapper design for embedded core test.
ITC 2000: 911-920 |
| 1999 |
|---|
| 5 | | Yervant Zorian,
Erik Jan Marinissen,
Rohit Kapur,
Tony Taylor,
Lee Whetsel:
Towards a standard for embedded core test: an example.
ITC 1999: 616-627 |
| 4 | | Yervant Zorian,
Erik Jan Marinissen,
Sujit Dey:
Testing Embedded-Core-Based System Chips.
IEEE Computer 32(6): 52-60 (1999) |
| 1998 |
|---|
| 3 | | Yervant Zorian,
Erik Jan Marinissen,
Sujit Dey:
Testing embedded-core based system chips.
ITC 1998: 130- |
| 2 | | Erik Jan Marinissen,
Robert G. J. Arendsen,
Gerard Bos,
Hans Dingemanse,
Maurice Lousberg,
Clemens Wouters:
A structured and scalable mechanism for test access to embedded reusable cores.
ITC 1998: 284-293 |
| 1 | | Joep Aerts,
Erik Jan Marinissen:
Scan chain design for test time reduction in core-based ICs.
ITC 1998: 448-457 |
