| 2012 | ||
|---|---|---|
| 185 | Tim Güneysu, Igor L. Markov, André Weimerskirch: Securely Sealing Multi-FPGA Systems. ARC 2012: 276-289 | |
| 184 | Kai-Hui Chang, Hong-Zu Chou, Igor L. Markov: RTL analysis and modifications for improving at-speed test. DATE 2012: 400-405 | |
| 183 | Myung-Chul Kim, Natarajan Viswanathan, Charles J. Alpert, Igor L. Markov, Shyam Ramji: MAPLE: multilevel adaptive placement for mixed-size designs. ISPD 2012: 193-200 | |
| 182 | Hadi Katebi, Karem A. Sakallah, Igor L. Markov: Conflict Anticipation in the Search for Graph Automorphisms. LPAR 2012: 243-257 | |
| 181 | Igor L. Markov, Mehdi Saeedi: Constant-Optimized Quantum Circuits for Modular Multiplication and Exponentiation CoRR abs/1202.6614: (2012) | |
| 180 | Myung-Chul Kim, Dongjin Lee, Igor L. Markov: SimPL: An Effective Placement Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 31(1): 50-60 (2012) | |
| 179 | Dongjin Lee, Igor L. Markov: Obstacle-Aware Clock-Tree Shaping During Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 31(2): 205-216 (2012) | |
| 178 | Johann Knechtel, Igor L. Markov, Jens Lienig: Assembling 2-D Blocks Into 3-D Chips. IEEE Trans. on CAD of Integrated Circuits and Systems 31(2): 228-241 (2012) | |
| 2011 | ||
| 177 | Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu: VLSI Physical Design - From Graph Partitioning to Timing Closure. Springer 2011: I-XI, 1-310 | |
| 176 | Igor L. Markov, Dongjin Lee: Algorithmic tuning of clock trees and derived non-tree structures. ICCAD 2011: 279-282 | |
| 175 | Dongjin Lee, Igor L. Markov: Multilevel tree fusion for robust clock networks. ICCAD 2011: 632-639 | |
| 174 | Myung-Chul Kim, Jin Hu, Dongjin Lee, Igor L. Markov: A SimPLR method for routability-driven placement. ICCAD 2011: 67-73 | |
| 173 | Dongjin Lee, Igor L. Markov: Obstacle-aware clock-tree shaping during placement. ISPD 2011: 123-130 | |
| 172 | Johann Knechtel, Igor L. Markov, Jens Lienig: Assembling 2D blocks into 3D chips. ISPD 2011: 81-88 | |
| 171 | Igor L. Markov, Yaoyun Shi: Constant-Degree Graph Expansions that Preserve Treewidth. Algorithmica 59(4): 461-470 (2011) | |
| 170 | Fadi A. Aloul, Igor L. Markov, Arathi Ramani, Karem A. Sakallah: Breaking Instance-Independent Symmetries In Exact Graph Coloring CoRR abs/1109.2347: (2011) | |
| 169 | Mehdi Saeedi, Igor L. Markov: Synthesis and Optimization of Reversible Circuits - A Survey CoRR abs/1110.2574: (2011) | |
| 168 | Igor L. Markov: EDA: Synergy or sum of the parts? [review of "Electronic Design Automation: Synthesis, Verification and Test (Systems on Silicon" (Wang, L.-T., Eds., et al; 2009)]. IEEE Design & Test of Computers 28(1): 78-79 (2011) | |
| 167 | Igor L. Markov: Getting Your Bits in Order. IEEE Design & Test of Computers 28(4): 98-101 (2011) | |
| 166 | David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov: Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. IEEE Micro 31(4): 51-62 (2011) | |
| 165 | Dongjin Lee, Igor L. Markov: CONTANGO: Integrated Optimization of SoC Clock Networks. VLSI Design 2011: (2011) | |
| 2010 | ||
| 164 | Raj R. Nadakuditi, Igor L. Markov: On the costs and benefits of stochasticity in stream processing. DAC 2010: 320-325 | |
| 163 | Dongjin Lee, Igor L. Markov: Contango: Integrated optimization of SoC clock networks. DATE 2010: 1468-1473 | |
| 162 | Héctor J. Garcia, Igor L. Markov: Spinto: High-performance energy minimization in spin glasses. DATE 2010: 160-165 | |
| 161 | Hadi Katebi, Igor L. Markov: Large-scale Boolean matching. DATE 2010: 771-776 | |
| 160 | David A. Papa, Smita Krishnaswamy, Igor L. Markov: SPIRE: A retiming-based physical-synthesis transformation system. ICCAD 2010: 373-380 | |
| 159 | Dongjin Lee, Myung-Chul Kim, Igor L. Markov: Low-power clock trees for CPUs. ICCAD 2010: 444-451 | |
| 158 | Myung-Chul Kim, Dongjin Lee, Igor L. Markov: SimPL: An effective placement algorithm. ICCAD 2010: 649-656 | |
| 157 | Jin Hu, Jarrod A. Roy, Igor L. Markov: Completing high-quality global routes. ISPD 2010: 35-41 | |
| 156 | Hadi Katebi, Karem A. Sakallah, Igor L. Markov: Symmetry and Satisfiability: An Update. SAT 2010: 113-127 | |
| 155 | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov, Alan Mishchenko: Logic synthesis and circuit customization using extensive external don't-cares. ACM Trans. Design Autom. Electr. Syst. 15(3): (2010) | |
| 154 | Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov: Ending Piracy of Integrated Circuits. IEEE Computer 43(10): 30-38 (2010) | |
| 153 | Igor L. Markov: Master numerical tasks with ease. IEEE Design & Test of Computers 27(1): 93-95 (2010) | |
| 152 | Igor L. Markov: Chips in 3D. IEEE Design & Test of Computers 27(4): 68-69 (2010) | |
| 151 | David A. Papa, Michael D. Moffitt, Charles J. Alpert, Igor L. Markov: Speeding Up Physical Synthesis with Transactional Timing Analysis. IEEE Design & Test of Computers 27(5): 14-25 (2010) | |
| 150 | Shigeru Yamashita, Igor L. Markov: Fast equivalence - checking for quantum circuits. Quantum Information & Computation 10(9&10): 721-734 (2010) | |
| 2009 | ||
| 149 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair Springer 2009: 3-185 | |
| 148 | George F. Viamontes, Igor L. Markov, John P. Hayes: Quantum Circuit Simulation. Springer 2009: I-X, 1-190 | |
| 147 | Smita Krishnaswamy, Igor L. Markov, John P. Hayes: Improving testability and soft-error resilience through retiming. DAC 2009: 508-513 | |
| 146 | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov: Customizing IP cores for system-on-chip designs using extensive external don't-cares. DATE 2009: 582-585 | |
| 145 | Jarrod A. Roy, Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov: CRISP: Congestion reduction by iterated spreading during placement. ICCAD 2009: 357-362 | |
| 144 | Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah: Dynamic symmetry-breaking for Boolean satisfiability. Ann. Math. Artif. Intell. 57(1): 59-73 (2009) | |
| 143 | Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco: Incremental Verification with Error Detection, Diagnosis, and Visualization. IEEE Design & Test of Computers 26(2): 34-43 (2009) | |
| 142 | Igor L. Markov: Book Review: A physical-design picture book. IEEE Design & Test of Computers 26(4): 100-101 (2009) | |
| 141 | Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes: Signature-Based SER Analysis and Design of Logic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 74-86 (2009) | |
| 140 | Jarrod A. Roy, Aaron N. Ng, Rajat Aggarwal, Venky Ramachandran, Igor L. Markov: Solving modern mixed-size placement instances. Integration 42(2): 262-275 (2009) | |
| 139 | Vivek V. Shende, Igor L. Markov: On the CNOT-cost of TOFFOLI gates. Quantum Information & Computation 9(5): 461-486 (2009) | |
| 2008 | ||
| 138 | Paul T. Darga, Karem A. Sakallah, Igor L. Markov: Faster symmetry discovery using sparsity of symmetries. DAC 2008: 149-154 | |
| 137 | Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov: Protecting bus-based hardware IP by secret sharing. DAC 2008: 846-851 | |
| 136 | Smita Krishnaswamy, Igor L. Markov, John P. Hayes: On the role of timing masking in reliable logic circuit design. DAC 2008: 924-929 | |
| 135 | Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov: EPIC: Ending Piracy of Integrated Circuits. DATE 2008: 1069-1074 | |
| 134 | Stephen Plaza, Igor L. Markov, Valeria Bertacco: Random Stimulus Generation using Entropy and XOR Constraints. DATE 2008: 664-669 | |
| 133 | Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov: Circuit CAD Tools as a Security Threat. HOST 2008: 65-66 | |
| 132 | Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David Blaauw: On the decreasing significance of large standard cells in technology mapping. ICCAD 2008: 116-121 | |
| 131 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Reap what you sow: spare cells for post-silicon metal fix. ISPD 2008: 103-110 | |
| 130 | Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov: The coming of age of (academic) global routing. ISPD 2008: 148-155 | |
| 129 | David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov: RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. ISPD 2008: 2-9 | |
| 128 | Stephen Plaza, Igor L. Markov, Valeria Bertacco: Optimizing non-monotonic interconnect using functional simulation and logic restructuring. ISPD 2008: 95-102 | |
| 127 | Jin Hu, Jarrod A. Roy, Igor L. Markov: Sidewinder: a scalable ILP-based router. SLIP 2008: 73-80 | |
| 126 | Andrew A. Kennings, Igor L. Markov: Circuit Placement. Encyclopedia of Algorithms 2008 | |
| 125 | Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes: Probabilistic transfer matrices in symbolic reliability analysis of logic circuits. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) | |
| 124 | Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov, Martha E. Pollack: Constraint-driven floorplan repair. ACM Trans. Design Autom. Electr. Syst. 13(4): (2008) | |
| 123 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Automating Postsilicon Debugging and Repair. IEEE Computer 41(7): 47-54 (2008) | |
| 122 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Fixing Design Errors With Counterexamples and Resynthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 184-188 (2008) | |
| 121 | Stephen Plaza, Igor L. Markov, Valeria Bertacco: Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2107-2119 (2008) | |
| 120 | David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov: RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2156-2168 (2008) | |
| 119 | Jarrod A. Roy, Igor L. Markov: High-Performance Routing at the Nanometer Scale. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1066-1077 (2008) | |
| 118 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: SafeResynth: A new technique for physical synthesis. Integration 41(4): 544-556 (2008) | |
| 117 | Ketan N. Patel, Igor L. Markov, John P. Hayes: Optimal synthesis of linear reversible circuits. Quantum Information & Computation 8(3): 282-294 (2008) | |
| 116 | Igor L. Markov, Yaoyun Shi: Simulating Quantum Computation by Contracting Tensor Networks. SIAM J. Comput. 38(3): 963-981 (2008) | |
| 115 | Jarrod A. Roy, David A. Papa, Igor L. Markov: Fine Control of Local Whitespace in Placement. VLSI Design 2008: (2008) | |
| 2007 | ||
| 114 | Jarrod A. Roy, Igor L. Markov: ECO-system: Embracing the Change in Placement. ASP-DAC 2007: 147-152 | |
| 113 | Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Node Mergers in the Presence of Don't Cares. ASP-DAC 2007: 414-419 | |
| 112 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Safe Delay Optimization for Physical Synthesis. ASP-DAC 2007: 628-633 | |
| 111 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Fixing Design Errors with Counterexamples and Resynthesis. ASP-DAC 2007: 944-949 | |
| 110 | Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes: Enhancing design robustness with reliability-aware resynthesis and logic simulation. ICCAD 2007: 149-154 | |
| 109 | Jarrod A. Roy, Igor L. Markov: High-performance routing at the nanometer scale. ICCAD 2007: 496-502 | |
| 108 | George F. Viamontes, Igor L. Markov, John P. Hayes: Checking equivalence of quantum circuits and states. ICCAD 2007: 69-74 | |
| 107 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Automating post-silicon debugging and repair. ICCAD 2007: 91-98 | |
| 106 | Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco: InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. ISQED 2007: 487-494 | |
| 105 | Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah: Symmetry breaking for pseudo-Boolean formulas. ACM Journal of Experimental Algorithmics 12: (2007) | |
| 104 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Postplacement rewiring by exhaustive search for functional symmetries. ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) | |
| 103 | Igor L. Markov, Yaoyun Shi: Constant-degree graph expansions that preserve the treewidth CoRR abs/0707.3622: (2007) | |
| 102 | Smita Krishnaswamy, Igor L. Markov, John P. Hayes: Tracking Uncertainty with Probabilistic Logic Circuit Testing. IEEE Design & Test of Computers 24(4): 312-321 (2007) | |
| 101 | Fadi A. Aloul, Arathi Ramani, Karem A. Sakallah, Igor L. Markov: Solution and Optimization of Systems of Pseudo-Boolean Constraints. IEEE Trans. Computers 56(10): 1415-1424 (2007) | |
| 100 | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov: Simulation-Based Bug Trace Minimization With BMC-Based Refinement. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 152-165 (2007) | |
| 99 | Jarrod A. Roy, Igor L. Markov: ECO-System: Embracing the Change in Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2173-2185 (2007) | |
| 98 | Jarrod A. Roy, Igor L. Markov: Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 632-644 (2007) | |
| 97 | Igor L. Markov, Louis Scheffer, Dirk Stroobandt: Special issue on System-Level Interconnect Prediction. Integration 40(4): 381 (2007) | |
| 2006 | ||
| 96 | David A. Papa, Igor L. Markov, Philip Chong: Utility of the OpenAccess database in academic research. ASP-DAC 2006: 440-441 | |
| 95 | Michael D. Moffitt, Aaron N. Ng, Igor L. Markov, Martha E. Pollack: Constraint-driven floorplan repair. DAC 2006: 1103-1108 | |
| 94 | Ramashis Das, Igor L. Markov, John P. Hayes: On-Chip Test Generation Using Linear Subspaces. European Test Symposium 2006: 111-116 | |
| 93 | Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky Ramachandran: Solving hard instances of floorplacement. ISPD 2006: 170-177 | |
| 92 | Jarrod A. Roy, David A. Papa, Aaron N. Ng, Igor L. Markov: Satisfying whitespace requirements in top-down placement. ISPD 2006: 206-208 | |
| 91 | Jarrod A. Roy, James F. Lu, Igor L. Markov: Seeing the forest and the trees: Steiner wirelength optimization in placemen. ISPD 2006: 78-85 | |
| 90 | Krysta Marie Svore, Alfred V. Aho, Andrew W. Cross, Isaac L. Chuang, Igor L. Markov: A Layered Software Architecture for Quantum Computing Design Tools. IEEE Computer 39(1): 74-83 (2006) | |
| 89 | Fadi A. Aloul, Karem A. Sakallah, Igor L. Markov: Efficient Symmetry Breaking for Boolean Satisfiability. IEEE Trans. Computers 55(5): 549-558 (2006) | |
| 88 | Vivek V. Shende, Stephen S. Bullock, Igor L. Markov: Synthesis of quantum-logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1000-1010 (2006) | |
| 87 | Jarrod A. Roy, Saurabh N. Adya, David A. Papa, Igor L. Markov: Min-cut floorplacement. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1313-1326 (2006) | |
| 86 | Saurabh N. Adya, Igor L. Markov, Paul G. Villarrubia: On whitespace and stability in physical synthesis. Integration 39(4): 340-362 (2006) | |
| 85 | Arathi Ramani, Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul: Breaking Instance-Independent Symmetries In Exact Graph Coloring. J. Artif. Intell. Res. (JAIR) 26: 289-322 (2006) | |
| 84 | Aditya K. Prasad, Vivek V. Shende, Igor L. Markov, John P. Hayes, Ketan N. Patel: Data structures and algorithms for simplifying reversible circuits. JETC 2(4): 277-293 (2006) | |
| 2005 | ||
| 83 | Igor L. Markov, Mike Hutton: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings ACM 2005 | |
| 82 | Vivek V. Shende, Stephen S. Bullock, Igor L. Markov: Synthesis of quantum logic circuits. ASP-DAC 2005: 272-275 | |
| 81 | Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah: Dynamic symmetry-breaking for improved Boolean optimization. ASP-DAC 2005: 445-450 | |
| 80 | Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes: Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices. DATE 2005: 282-287 | |
| 79 | Igor L. Markov, Dmitri Maslov: Uniformly-Switching Logic for Cryptographic Hardware. DATE 2005: 432-433 | |
| 78 | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov: Simulation-based bug trace minimization with BMC-based refinement. ICCAD 2005: 1045-1051 | |
| 77 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. ICCAD 2005: 56-63 | |
| 76 | Hayward H. Chan, Saurabh N. Adya, Igor L. Markov: Are floorplan representations important in digital design? ISPD 2005: 129-136 | |
| 75 | Jarrod A. Roy, David A. Papa, Saurabh N. Adya, Hayward H. Chan, Aaron N. Ng, James F. Lu, Igor L. Markov: Capo: robust and scalable open-source min-cut floorplacer. ISPD 2005: 224-226 | |
| 74 | Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov: Early research experience with OpenAccess gear: an open source development environment for physical design. ISPD 2005: 94-100 | |
| 73 | Aaron N. Ng, Igor L. Markov: Toward Quality EDA Tools and Tool Flows Through High-Performance Computing. ISQED 2005: 22-27 | |
| 72 | Saurabh N. Adya, Igor L. Markov: Combinatorial techniques for mixed-size placement. ACM Trans. Design Autom. Electr. Syst. 10(1): 58-90 (2005) | |
| 71 | DoRon B. Motter, Jarrod A. Roy, Igor L. Markov: Resolution cannot polynomially simulate compressed-BFS. Ann. Math. Artif. Intell. 44(1-2): 121-156 (2005) | |
| 70 | Vivek V. Shende, Igor L. Markov: Quantum circuits for incompletely specified two-qubit operators. Quantum Information & Computation 5(1): 49-57 (2005) | |
| 69 | George F. Viamontes, Igor L. Markov, John P. Hayes: Graph-based simulation of quantum computation in the density matrix representation. Quantum Information & Computation 5(2): 113-130 (2005) | |
| 2004 | ||
| 68 | Louis Scheffer, Igor L. Markov: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings ACM 2004 | |
| 67 | David A. Papa, Saurabh N. Adya, Igor L. Markov: Constructive benchmarking for placement. ACM Great Lakes Symposium on VLSI 2004: 113-118 | |
| 66 | Andrew B. Kahng, Igor L. Markov, Sherief Reda: On legalization of row-based placements. ACM Great Lakes Symposium on VLSI 2004: 214-219 | |
| 65 | Hayward H. Chan, Igor L. Markov: Practical slicing and non-slicing block-packing without simulated annealing. ACM Great Lakes Symposium on VLSI 2004: 282-287 | |
| 64 | Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah: ShatterPB: symmetry-breaking for pseudo-Boolean formulas. ASP-DAC 2004: 883-886 | |
| 63 | Arathi Ramani, Igor L. Markov: Automatically Exploiting Symmetries in Constraint Programming. CSCLP 2004: 98-112 | |
| 62 | Yoonna Oh, Maher N. Mneimneh, Zaher S. Andraus, Karem A. Sakallah, Igor L. Markov: AMUSE: a minimally-unsatisfiable subformula extractor. DAC 2004: 518-523 | |
| 61 | Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah, Igor L. Markov: Exploiting structure in symmetry detection for CNF. DAC 2004: 530-534 | |
| 60 | Andrew B. Kahng, Igor L. Markov, Sherief Reda: Boosting: Min-Cut Placement with Improved Signal Delay. DATE 2004: 1098-1103 | |
| 59 | George F. Viamontes, Igor L. Markov, John P. Hayes: High-Performance QuIDD-Based Simulation of Quantum Circuits. DATE 2004: 1354-1355 | |
| 58 | Arathi Ramani, Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah: Breaking Instance-Independent Symmetries in Exact Graph Coloring. DATE 2004: 324-331 | |
| 57 | Vivek V. Shende, Igor L. Markov, Stephen S. Bullock: Smaller Two-Qubit Circuits for Quantum Communication and Computation. DATE 2004: 980-987 | |
| 56 | Saurabh N. Adya, S. Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov: Unification of partitioning, placement and floorplanning. ICCAD 2004: 550-557 | |
| 55 | Ketan N. Patel, Igor L. Markov: Error-correction and crosstalk avoidance in DSM busses. IEEE Trans. VLSI Syst. 12(10): 1076-1080 (2004) | |
| 54 | Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden: Benchmarking for large-scale placement and beyond. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 472-487 (2004) | |
| 53 | Ketan N. Patel, John P. Hayes, Igor L. Markov: Fault testing for reversible circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1220-1230 (2004) | |
| 52 | Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah: MINCE: A Static Global Variable-Ordering Heuristic for SAT Search and BDD Manipulation. J. UCS 10(12): 1562-1596 (2004) | |
| 51 | Stephen S. Bullock, Igor L. Markov: Asymptotically optimal circuits for arbitrary n-qubit diagonal comutations. Quantum Information & Computation 4(1): 27-47 (2004) | |
| 2003 | ||
| 50 | Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah: FORCE: a fast and easy-to-implement variable-ordering heuristic. ACM Great Lakes Symposium on VLSI 2003: 116-119 | |
| 49 | Stephen S. Bullock, Igor L. Markov: An arbitrary twoqubit computation In 23 elementary gates or less. DAC 2003: 324-329 | |
| 48 | Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah: Shatter: efficient symmetry-breaking for boolean satisfiability. DAC 2003: 836-839 | |
| 47 | Saurabh N. Adya, Igor L. Markov, Paul Villarrubia: On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis. ICCAD 2003: 311-319 | |
| 46 | Arathi Ramani, Igor L. Markov: Combining Two Local Search Approaches to Hypergraph Partitioning. IJCAI 2003: 1546- | |
| 45 | Fadi A. Aloul, Karem A. Sakallah, Igor L. Markov: Efficient Symmetry Breaking for Boolean Satisfiability. IJCAI 2003: 271-276 | |
| 44 | Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden: Benchmarking for large-scale placement and beyond. ISPD 2003: 95-103 | |
| 43 | Andrew B. Kahng, Igor L. Markov: Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint. ISQED 2003: 208-213 | |
| 42 | Ketan N. Patel, Igor L. Markov: Error-correction and crosstalk avoidance in DSM busses. SLIP 2003: 9-14 | |
| 41 | Ketan N. Patel, John P. Hayes, Igor L. Markov: Fault Testing for Reversible Circuits. VTS 2003: 410-416 | |
| 40 | Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester: Improved a priori interconnect predictions and technology extrapolation in the GTX system. IEEE Trans. VLSI Syst. 11(1): 3-14 (2003) | |
| 39 | Saurabh N. Adya, Igor L. Markov: Fixed-outline floorplanning: enabling hierarchical design. IEEE Trans. VLSI Syst. 11(6): 1120-1135 (2003) | |
| 38 | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Hierarchical whitespace allocation in top-down placement. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1550-1556 (2003) | |
| 37 | Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes: Synthesis of reversible logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 710-722 (2003) | |
| 36 | Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah: Solving difficult instances of Boolean satisfiability in the presence of symmetry. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1117-1137 (2003) | |
| 2002 | ||
| 35 | DoRon B. Motter, Igor L. Markov: A Compressed Breadth-First Search for Satisfiability. ALENEX 2002: 29-42 | |
| 34 | Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah: Solving difficult SAT instances in the presence of symmetry. DAC 2002: 731-736 | |
| 33 | Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes: Reversible logic circuit synthesis. ICCAD 2002: 353-360 | |
| 32 | Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah: Generic ILP versus specialized 0-1 ILP: an update. ICCAD 2002: 450-457 | |
| 31 | Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah: Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering. ICCD 2002: 64-69 | |
| 30 | Saurabh N. Adya, Igor L. Markov: Consistent placement of macro-blocks using floorplanning and standard-cell placement. ISPD 2002: 12-17 | |
| 29 | Andrew B. Kahng, Stefanus Mantik, Igor L. Markov: Min-max placement for large-scale timing optimization. ISPD 2002: 143-148 | |
| 28 | Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes: Reversible Logic Circuit Synthesis. IWLS 2002: 125-130 | |
| 27 | Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah: Efficient Gate and Input Ordering for Circuit-to-BDD Conversion. IWLS 2002: 137-142 | |
| 26 | DoRon B. Motter, Igor L. Markov: Overcoming Resolution-Based Lower Bounds for SAT Solvers. IWLS 2002: 373-378 | |
| 25 | Andrew E. Caldwell, Igor L. Markov: Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms. IEEE Design & Test of Computers 19(3): 72-81 (2002) | |
| 2001 | ||
| 24 | Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah: Faster SAT and Smaller BDDs via Common Function Structure. ICCAD 2001: 443-448 | |
| 23 | Saurabh N. Adya, Igor L. Markov: Fixed-outline Floorplanning through Better Local Search. ICCD 2001: 328-334 | |
| 22 | Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe: Constraint-based watermarking techniques for design IP protection. IEEE Trans. on CAD of Integrated Circuits and Systems 20(10): 1236-1252 (2001) | |
| 2000 | ||
| 21 | Andrew A. Kennings, Igor L. Markov: Analytical minimization of half-perimeter wirelength. ASP-DAC 2000: 179-184 | |
| 20 | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Improved algorithms for hypergraph bipartitioning. ASP-DAC 2000: 661-666 | |
| 19 | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Can recursive bisection alone produce routable placements? DAC 2000: 477-482 | |
| 18 | Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester: GTX: the MARCO GSRC technology extrapolation system. DAC 2000: 693-698 | |
| 17 | Olivier Coudert, Igor L. Markov, Christoph Meinel, Ellen Sentovich: Web-based frameworks to enable CAD RD (abstract). DAC 2000: 711 | |
| 16 | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning. ACM Journal of Experimental Algorithmics 5: 5 (2000) | |
| 15 | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Optimal partitioners and end-case placers for standard-cell layout. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1304-1313 (2000) | |
| 14 | Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Hypergraph partitioning with fixed vertices [VLSI CAD]. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 267-272 (2000) | |
| 1999 | ||
| 13 | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning. ALENEX 1999: 177-193 | |
| 12 | Ross Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov: Function Smoothing with Applications to VLSI Layout. ASP-DAC 1999: 225- | |
| 11 | Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov: Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. DAC 1999: 349-354 | |
| 10 | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Hypergraph Partitioning with Fixed Vertices. DAC 1999: 355-359 | |
| 9 | Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Partitioning with terminals: a "new" problem and new benchmarks. ISPD 1999: 151-157 | |
| 8 | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Optimal partitioners and end-case placers for standard-cell layout. ISPD 1999: 90-96 | |
| 7 | Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky: On wirelength estimations for row-based placement. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1265-1278 (1999) | |
| 1998 | ||
| 6 | Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe: Watermarking Techniques for Intellectual Property Protection. DAC 1998: 776-781 | |
| 5 | Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe: Robust IP Watermarking Methodologies for Physical Design. DAC 1998: 782-787 | |
| 4 | Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky: On wirelength estimations for row-based placement. ISPD 1998: 4-11 | |
| 3 | Charles J. Alpert, Tony F. Chan, Andrew B. Kahng, Igor L. Markov, Pep Mulet: Faster minimization of linear wirelength for global placement. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 3-13 (1998) | |
| 1997 | ||
| 2 | Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Igor L. Markov, Kenneth Yan: Quadratic Placement Revisited. DAC 1997: 752-757 | |
| 1 | Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan: Faster minimization of linear wirelength for global placement. ISPD 1997: 4-11 | |
Colors in the list of coauthors
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