Kazuya Masu

	2009
35		Hirotaka Sugawara, Kenichi Okada, Kazuya Masu: Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit. IEICE Transactions 92-A(2): 401-410 (2009)
34		Takumi Uezono, Takashi Sato, Kazuya Masu: One-Shot Voltage-Measurement Circuit Utilizing Process Variation. IEICE Transactions 92-A(4): 1024-1030 (2009)
33		Shiho Hagiwara, Takashi Sato, Kazuya Masu: Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits. IEICE Transactions 92-A(4): 1031-1038 (2009)
32		Koh Yamanaga, Takashi Sato, Kazuya Masu: 2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept. IEICE Transactions 92-A(4): 976-982 (2009)
	2008
31		Susumu Sadoshima, Satoshi Fukuda, Tackya Yammouch, Hiroyuki Ito, Kenichi Okada, Kazuya Masu: Small-area CMOS RF distributed mixer using multi-port inductors. ASP-DAC 2008: 105-106
30		Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu: Determination of optimal polynomial regression function to decompose on-die systematic and random variations. ASP-DAC 2008: 518-523
29		Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu: LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process. ASP-DAC 2008: 97-98
28		Masanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu: Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution. DAC 2008: 698-701
27		Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu: Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network. IEICE Transactions 91-A(4): 951-956 (2008)
26		Masanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu: An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis. IEICE Transactions 91-A(4): 957-964 (2008)
25		Kazuya Masu, Kenichi Okada: Reconfigurable RF CMOS Circuit for Cognitive Radio. IEICE Transactions 91-B(1): 10-13 (2008)
24		Kenta Yamada, Takashi Sato, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu, Shigetaka Kumashiro: Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress. IEICE Transactions 91-C(7): 1142-1150 (2008)
	2007
23		Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu: Improvement of power distribution network using correlation-based regression analysis. ACM Great Lakes Symposium on VLSI 2007: 513-516
22		Satoshi Fukuda, D. Kawazoe, Kenichi Okada, Kazuya Masu: Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation. ASP-DAC 2007: 104-105
21		Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu: A Multi-Drop Transmission-Line Interconnect in Si LSI. ASP-DAC 2007: 118-119
20		K. Ohashi, Y. Ito, Yoshiaki Yoshihara, Kenichi Okada, Kazuya Masu: A Wideband CMOS LC-VCO Using Variable Inductor. ASP-DAC 2007: 98-99
19		Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu: A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. ISQED 2007: 21-26
18		Takashi Sato, Shiho Hagiwara, Takumi Uezono, Kazuya Masu: Weakness Identification for Effective Repair of Power Distribution Network. PATMOS 2007: 222-231
17		Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu: Adaptable wire-length distribution with tunable occupation probability. SLIP 2007: 1-8
16		Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Tatsuya Ito, Kazuhisa Itoi, Masakazu Sato, Ryozo Yamauchi, Kazuya Masu: Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology. IEICE Transactions 90-C(3): 641-643 (2007)
	2006
15		D. Kawazoe, Hirotaka Sugawara, Tatsuya Ito, Kenichi Okada, Kazuya Masu: Reconfigurable CMOS low noise amplifier for self compensation. ISCAS 2006
14		Takumi Uezono, Kenichi Okada, Kazuya Masu: Via Distribution Model for Yield Estimation. ISQED 2006: 479-484
13		Kenichi Okada, Takumi Uezono, Kazuya Masu: Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology. PATMOS 2006: 181-190
12		Takumi Uezono, Kenichi Okada, Kazuya Masu: Statistical Modeling of a Via Distribution for Yield Estimation. IEICE Transactions 89-A(12): 3579-3584 (2006)
11		Kazuya Masu, Kenichi Okada, Hiroyuki Ito: RF Passive Components Using Metal Line on Si CMOS. IEICE Transactions 89-C(6): 681-691 (2006)
	2005
10		Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu: Evaluation of on-chip transmission line interconnect using wire length distribution. ASP-DAC 2005: 133-138
9		Kenichi Okada, Yoshiaki Yoshihara, Hirotaka Sugawara, Kazuya Masu: A dynamic reconfigurable RF circuit architecture. ASP-DAC 2005: 683-686
8		Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu: Wire Length Distribution Model Considering Core Utilization for System on Chip. ISVLSI 2005: 276-277
7		Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu: Prediction of delay time for future LSI using on-chip transmission line interconnects. SLIP 2005: 7-12
6		Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu: Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model. IEICE Transactions 88-A(12): 3358-3366 (2005)
5		Hidenari Nakashima, Naohiro Takagi, Junpei Inoue, Kenichi Okada, Kazuya Masu: Evaluation of X Architecture Using Interconnect Length Distribution. IEICE Transactions 88-A(12): 3437-3444 (2005)
4		Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu: Wire Length Distribution Model for System LSI. IEICE Transactions 88-A(12): 3445-3452 (2005)
3		Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu: Wide Tuning Range LC-VCO Using Variable Inductor for Reconfigurable RF Circuit. IEICE Transactions 88-A(2): 507-512 (2005)
	2004
2		Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu: ULSI Interconnect Length Distribution Model Considering Core Utilization. DATE 2004: 1210-1217
1		Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu: Inductance-Tuned LC-VCO for Reconfigurable RF Circuit Design. IEICE Electronic Express 1(7): 156-159 (2004)

Coauthor Index

1	Shuhei Amakawa	[17] [19] [24]
2	Satoshi Fukuda	[22] [31]
3	Shinichiro Gomi	[10]
4	Shiho Hagiwara	[18] [19] [23] [27] [33]
5	Masanori Imai	[26] [28]
6	Junpei Inoue	[2] [4] [5] [6] [7] [8] [10]
7	Takahiro Ishii	[29]
8	Hiroyuki Ito	[1] [3] [10] [11] [16] [21] [29] [31]
9	Tatsuya Ito	[15] [16]
10	Y. Ito	[20]
11	Kazuhisa Itoi	[16]
12	D. Kawazoe	[15] [22]
13	Shigetaka Kumashiro	[24]
14	Takanori Kyogoku	[4] [7] [8] [10]
15	Akiko Mineyama	[29]
16	Hidenari Nakashima	[2] [4] [5] [6] [8]
17	Noriaki Nakayama	[19] [24] [26] [28] [30]
18	K. Ohashi	[20]
19	Kenichi Okada	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [19] [20] [21] [22] [25] [29] [31] [35]
20	Susumu Sadoshima	[31]
21	Masakazu Sato	[16]
22	Takashi Sato	[17] [18] [19] [21] [23] [24] [26] [27] [28] [30] [32] [33] [34]
23	Junki Seita	[21]
24	Hirotaka Sugawara	[1] [3] [9] [15] [35]
25	Hideyuki Sugita	[16]
26	Naohiro Takagi	[5]
27	Hiroyuki Ueyama	[30]
28	Takumi Uezono	[4] [7] [8] [10] [12] [13] [14] [17] [18] [19] [23] [27] [34]
29	Kenta Yamada	[24]
30	Koh Yamanaga	[32]
31	Ryozo Yamauchi	[16]
32	Tackya Yammouch	[31]
33	Yoshiaki Yoshihara	[1] [3] [9] [20]