Hiroo Masuda

	2009
20		Hiroo Masuda, Takeshi Kida, Shin-ichi Ohkawa: Comprehensive Matching Characterization of Analog CMOS Circuits. IEICE Transactions 92-A(4): 966-975 (2009)
19		Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato: Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations. IEICE Transactions 92-A(4): 990-997 (2009)
	2008
18		Shin-ichi Ohkawa, Hiroo Masuda, Yasuaki Inoue: A Novel Expression of Spatial Correlation by a Random Curved Surface Model and Its Application to LSI Design. IEICE Transactions 91-A(4): 1062-1070 (2008)
17		Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda: Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis. IEICE Transactions 91-C(4): 647-654 (2008)
	2006
16		Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda: Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills. IEICE Transactions 89-A(4): 847-855 (2006)
15		Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue: Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays. IEICE Transactions 89-A(4): 856-864 (2006)
	2005
14		Hiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki: Approach for physical design in sub-100 nm era. ISCAS (6) 2005: 5934-5937
13		Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture. ISQED 2005: 153-158
12		Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. ISQED 2005: 586-591
11		Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda: A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills. IEICE Transactions 88-A(11): 3180-3187 (2005)
10		Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda: Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Transactions 88-A(12): 3453-3462 (2005)
9		Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills. IEICE Transactions 88-A(12): 3471-3478 (2005)
8		Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda: Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an Lsi Chip. IEICE Transactions 88-C(5): 788-795 (2005)
	2004
7		Chieki Mizuta, Jiro Iwai, Ken Machida, Tetsuro Kage, Hiroo Masuda: Large-scale linear circuit simulation with an inversed inductance matrix. ASP-DAC 2004: 511-516
6		Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda: DEPOGIT: dense power-ground interconnect architecture for physical design integrity. ASP-DAC 2004: 517-522
	2003
5		Takashi Sato, Hiroo Masuda: Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay. ISQED 2003: 395-400
	1998
4		Hiroo Masuda, Katsumi Tsuneno, Hisako Sato, Kazutaka Mori: TCAD/DA for MPU and ASIC Development. ASP-DAC 1998: 129-134
	1991
3		Hiroo Masuda, Jun'ichi Mano, Ryuichi Ikematsu, Hitoshi Sugihara, Yukio Aoki: A submicrometer MOS transistor I-V model for circuit simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 10(2): 161-170 (1991)
	1988
2		Hiroo Masuda, Yukio Aoki, Jun'ichi Mano, Osamu Yamashiro: MOSTSM: a physically based charge conservative MOSFET model. IEEE Trans. on CAD of Integrated Circuits and Systems 7(12): 1229-1236 (1988)
	1987
1		Yukio Aoki, Hiroo Masuda, Shozo Shimada, Shoji Sato: A New Design-Centering Methodology for VLSI Device Development. IEEE Trans. on CAD of Integrated Circuits and Systems 6(3): 452-461 (1987)

Coauthor Index

1	Masakazu Aoki	[8] [14] [17]
2	Yukio Aoki	[1] [2] [3]
3	Wei Fong Chang	[9] [12]
4	Junko Fujii	[15]
5	Masanori Hashimoto	[10] [19]
6	Zhangcai Huang	[10] [15] [16]
7	Tetsuya Ibe	[9] [12]
8	Ryuichi Ikematsu	[3]
9	Ryosuke Inagaki	[10]
10	Toshinori Inoshita	[15]
11	Yasuaki Inoue	[9] [10] [11] [12] [13] [15] [16] [18]
12	Jiro Iwai	[7]
13	Tetsuro Kage	[6] [7] [9] [12] [13]
14	Toshiki Kanamoto	[9] [11] [12] [16] [19]
15	Akira Kasebe	[9] [10] [11] [12] [15] [16]
16	Takeshi Kida	[20]
17	Atsushi Kurokawa	[6] [9] [10] [11] [12] [13] [15] [16] [19]
18	Ken Machida	[7]
19	Jun'ichi Mano	[2] [3]
20	Chieki Mizuta	[7]
21	Kazutaka Mori	[4]
22	Hidenari Nakashima	[19]
23	Shin-ichi Ohkawa	[8] [14] [17] [18] [20]
24	Takaaki Okumura	[19]
25	Nobuto Ono	[6] [13] [19]
26	Tsuyoshi Sakata	[19]
27	Hisako Sato	[4]
28	Shoji Sato	[1]
29	Takashi Sato	[5] [19]
30	Shozo Shimada	[1]
31	Hitoshi Sugihara	[3]
32	Hiroshi Takafuji	[19]
33	Katsumi Tsuneno	[4]
34	Masaharu Yamamoto	[13]
35	Osamu Yamashiro	[2]
36	Yun Yang	[10] [16]

Colors in the list of coauthors