Jimson Mathew

	2009
29		Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty, Jimson Mathew: Single ended 6T SRAM with isolated read-port for low-power embedded systems. DATE 2009: 917-922
28		Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan: Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. VLSI Design 2009: 307-312
	2008
27		Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan: De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. DATE 2008: 1370-1373
26		Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan: Fault tolerant bit parallel finite field multipliers using LDPC codes. ISCAS 2008: 1684-1687
25		Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan: A nano-CMOS process variation induced read failure tolerant SRAM cell. ISCAS 2008: 3334-3337
24		Yi Xin Su, Jimson Mathew, Jawar Singh, Dhiraj K. Pradhan: Pseudo parallel architecture for AES with error correction. SoCC 2008: 187-190
23		Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. SoCC 2008: 243-246
22		Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: Failure analysis for ultra low power nano-CMOS SRAM under process variations. SoCC 2008: 251-254
21		Donny Cheung, Dmitri Maslov, Jimson Mathew, Dhiraj K. Pradhan: On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography. TQC 2008: 96-104
20		Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan: Single Error Correcting Finite Field Multipliers Over GF(2m). VLSI Design 2008: 33-38
19		Jimson Mathew, Hafizur Rahaman, Babita R. Jose, Dhiraj K. Pradhan: Design of Reversible Finite Field Arithmetic Circuits with Error Detection. VLSI Design 2008: 453-459
18		Jimson Mathew, Hafizur Rahaman, A. K. Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan: A Galois Field Based Logic Synthesis Approach with Testability. VLSI Design 2008: 629-634
17		Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir: C-testable bit parallel multipliers over GF(2m). ACM Trans. Design Autom. Electr. Syst. 13(1): (2008)
16		Babita R. Jose, P. Mythili, Jimson Mathew: GA-based Optimization of Sigma-delta Modulators for Wireless Transceivers. Engineering Letters 16(4): 473-479 (2008)
15		Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir: Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m). IEEE Trans. Computers 57(9): 1289-1294 (2008)
14		Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew: GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 698-711 (2008)
13		Jimson Mathew, R. Mahesh, A. Prasad Vinod, Edmund Ming-Kit Lai: Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation Specifications for Wireless Communication Receivers. IEICE Transactions 91-A(9): 2564-2570 (2008)
	2007
12		Babita R. Jose, P. Mythili, Jawar Singh, Jimson Mathew: A Triple-Mode Sigma-Delta Modulator Design for Wireless Standards. ICIT 2007: 127-132
11		Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan: Single Event Upset Detection and Correction. ICIT 2007: 13-18
10		Jimson Mathew, Hafizur Rahaman, Dhiraj K. Pradhan: Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. IOLTS 2007: 207-208
9		Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. ISCAS 2007: 141-144
8		R. Stapenhurst, K. Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan: On the Hardware Reduction of z-Datapath of Vectoring CORDIC. ISCAS 2007: 3002-3005
7		Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. ISCAS 2007: 3675-3678
6		Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. ISQED 2007: 380-385
5		Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan: Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). VLSI Design 2007: 479-484
4		Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan: Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). VTS 2007: 422-430
	2006
3		Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew: An efficient technique for synthesis and optimization of polynomials in GF(2m). ICCAD 2006: 151-157
	2002
2		Jimson Mathew, Elena Dubrova: Self-Checking 1-out-of-n CMOS Current-Mode Checker. DFT 2002: 69-77
	1999
1		Jimson Mathew, D. Radhakrishnan, T. Srikanthan: Residue-to-binary arithmetic converter for moduli set {2n -1, 2n, 2n+1, 2n+1 -1}. NSIP 1999: 185-188

Coauthor Index

1	Costas Argyrides	[20]
2	Donny Cheung	[21]
3	Elena Dubrova	[2]
4	Simon Hollis	[29]
5	Mohammad Hosseinabady	[11] [26] [27]
6	Abusaleh M. Jabir	[3] [14] [15] [17] [18] [20] [26]
7	Babita R. Jose	[12] [16] [19]
8	Mohammad Reza Kakoee	[27]
9	Edmund Ming-Kit Lai	[13]
10	K. Maharatna	[8]
11	R. Mahesh	[13]
12	Dmitri Maslov	[21]
13	Seyed Ghassem Miremadi	[6] [7] [9]
14	Saraju P. Mohanty	[22] [23] [25] [28] [29]
15	P. Mythili	[12] [16]
16	José L. Núñez-Yáñez	[8]
17	Dhiraj K. Pradhan	[3] [4] [5] [6] [7] [8] [9] [10] [11] [14] [15] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29]
18	D. Radhakrishnan	[1]
19	Hafizur Rahaman	[4] [5] [10] [15] [17] [18] [19] [20]
20	Biplab K. Sikdar	[4]
21	A. K. Singh	[18]
22	Jawar Singh	[11] [12] [22] [23] [24] [25] [26] [28] [29]
23	T. Srikanthan	[1]
24	R. Stapenhurst	[8]
25	Yi Xin Su	[24]
26	A. Prasad Vinod	[13]
27	Hamid R. Zarandi	[6] [7] [9]

Colors in the list of coauthors