William H. McAnney

	1992
16		Jacob Savir, William H. McAnney: A Multiple Seed Linear Feedback Shift Register. IEEE Trans. Computers 41(2): 250-252 (1992)
	1991
15		Jacob Savir, William H. McAnney, Salvatore R. Vecchio: Testing for Coupled Cells in Random-Access Memories. IEEE Trans. Computers 40(10): 1177-1180 (1991)
	1989
14		Jacob Savir, William H. McAnney, Salvatore R. Vecchio: Testing for Coupled Cells in Random-Access Memories. ITC 1989: 439-451
	1988
13		Jacob Savir, William H. McAnney: Identification of Failing Tests with Cycling Registers. ITC 1988: 322-328
12		Jacob Savir, William H. McAnney: Random Pattern Testability of Delay Faults. IEEE Trans. Computers 37(3): 291-300 (1988)
11		William H. McAnney, Jacob Savir: Built-In Checking of the Correct Self-Test Signature. IEEE Trans. Computers 37(9): 1142-1145 (1988)
	1987
10		Jacob Savir, William H. McAnney, Salvatore R. Vecchio: Fault Propagation Through Embedded Multiport Memories. IEEE Trans. Computers 36(5): 592-602 (1987)
	1986
9		Jacob Savir, William H. McAnney: Random Pattern Testability of Delay Faults. ITC 1986: 263-273
8		William H. McAnney, Jacob Savir: Built-In Checking of the Correct Self-Test Signature. ITC 1986: 54-59
7		Paul H. Bardell, William H. McAnney: Pseudorandom Arrays for Built-In Tests. IEEE Trans. Computers 35(7): 653-658 (1986)
	1985
6		Jacob Savir, William H. McAnney, Salvatore R. Vecchio: Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory. ITC 1985: 100-105
5		Jacob Savir, William H. McAnney, Salvatore R. Vecchio: Random Pattern Testing for Address-Line Faults in an Embedded Multiport Memory. ITC 1985: 106-114
4		Paul H. Bardell, William H. McAnney: Self-Test of Random Access Memories. ITC 1985: 352-355
	1984
3		William H. McAnney, Paul H. Bardell, V. P. Gupta: Random Testing for Stuck-At Storage Cells in an Embedded Memory. ITC 1984: 157-166
2		Paul H. Bardell, William H. McAnney: Parallel Pseudorandom Sequences for Built-In Test. ITC 1984: 302-308
	1982
1		Paul H. Bardell, William H. McAnney: Self-Testing of Multichip Logic Modules. ITC 1982: 200-204

Coauthor Index

1	Paul H. Bardell	[1] [2] [3] [4] [7]
2	V. P. Gupta	[3]
3	Jacob Savir	[5] [6] [8] [9] [10] [11] [12] [13] [14] [15] [16]
4	Salvatore R. Vecchio	[5] [6] [10] [14] [15]