 | 2008 |
|---|
| 8 |       | Kieran McLaughlin,
Sakir Sezer,
Holger Blume,
Xin Yang,
Friederich Kupzog,
Tobias G. Noll:
A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling.
IEEE Trans. VLSI Syst. 16(7): 781-791 (2008) |
| 2007 |
|---|
| 7 | | Ciaran Toal,
Dwayne Burns,
Kieran McLaughlin,
Sakir Sezer,
Stephen O'Kane:
An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing.
AHS 2007: 613-618 |
| 6 | | Kieran McLaughlin,
Sakir Sezer:
High-Speed IP Address Lookups Using Hardware Based Tree Structures.
AHS 2007: 625-632 |
| 5 | | Dwayne Burns,
Ciaran Toal,
Kieran McLaughlin,
Sakir Sezer,
Mike Hutton,
Kevin Cackovic:
An FPGA Based Memory Efficient Shared Buffer Implementation.
FPL 2007: 661-664 |
| 2006 |
|---|
| 4 | | Friederich Kupzog,
Holger Blume,
Tobias G. Noll,
Kieran McLaughlin,
Sakir Sezer,
John V. McCanny:
Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup.
AICT/ICIW 2006: 56 |
| 3 | | Kieran McLaughlin,
Niall O'Connor,
Sakir Sezer:
Exploring CAM Design For Network Processing Using FPGA Technology.
AICT/ICIW 2006: 84 |
| 2 | | Kieran McLaughlin,
Friederich Kupzog,
Holger Blume,
Sakir Sezer,
Tobias G. Noll,
John V. McCanny:
Design and analysis of matching circuit architectures for a closest match lookup.
IPDPS 2006 |
| 2005 |
|---|
| 1 | | Kieran McLaughlin,
Stephen O'Kane,
Sakir Sezer:
Implementing High Speed IP Address Lookups in Hardware.
AICT/SAPIR/ELETE 2005: 140-144 |
