 | 2009 |
| 19 |  | Jose Antonio Valero,
Julio Septién,
Daniel Mozos,
Hortensia Mecha:
3D FPGA resource management and fragmentation metric for hardware multitasking.
IPDPS 2009: 1-7 |
| 2008 |
| 18 |  | Angel Luis González Bravo,
Hortensia Mecha,
Julio Septién,
Sara Román Navarro,
Daniel Mozos:
Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system.
ERSA 2008: 307-308 |
| 17 |  | Laura Sanchez,
Julio Septién,
Daniel Mozos,
Hortensia Mecha,
Angel Luis González Bravo:
FPGA Resource Management Using Internal RAM as Aata Cache.
ERSA 2008: 317-318 |
| 16 |  | Jose Antonio Valero,
Julio Septién,
Daniel Mozos,
Hortensia Mecha,
Angel Luis González Bravo:
Resource Management for Hw Multitasking in Three Dimensional FPGAs.
ERSA 2008: 319-320 |
| 15 |  | Julio Septién,
Daniel Mozos,
Hortensia Mecha,
Jesús Tabero,
Miguel Angel García de Dios:
Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking.
IPDPS 2008: 1-8 |
| 14 |  | Jesús Tabero,
Julio Septién,
Hortensia Mecha,
Daniel Mozos:
Allocation heuristics and defragmentation measures for reconfigurable systems management.
Integration 41(2): 281-296 (2008) |
| 2006 |
| 13 |  | Sara Román Navarro,
Julio Septién,
Hortensia Mecha,
Daniel Mozos:
Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs.
ARC 2006: 187-192 |
| 12 |  | Jesús Tabero,
Julio Septién,
Hortensia Mecha,
Daniel Mozos:
Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems.
ASP-DAC 2006: 396-401 |
| 11 |  | Sara Román Navarro,
Hortensia Mecha,
Daniel Mozos,
Julio Septién:
Partition Based Dynamic 2D HW Multitasking Management.
DSD 2006: 61-70 |
| 10 |  | Julio Septién,
Hortensia Mecha,
Daniel Mozos,
Jesús Tabero:
2D defragmentation heuristics for hardware multitasking on reconfigurable devices.
IPDPS 2006 |
| 2004 |
| 9 |  | Jesús Tabero,
Julio Septién,
Hortensia Mecha,
Daniel Mozos:
A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management.
FPL 2004: 241-250 |
| 2003 |
| 8 |  | Javier Resano,
Daniel Mozos,
Elena Pérez-Miñana,
Hortensia Mecha,
Julio Septién:
A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements.
PATMOS 2003: 580-589 |
| 7 |  | Javier Resano,
M. Elena Pérez,
Daniel Mozos,
Hortensia Mecha,
Julio Septién:
Analyzing communication overheads during hardware/software partitioning.
Microelectronics Journal 34(11): 1001-1007 (2003) |
| 1999 |
| 6 |  | Katzalin Olcoz,
Francisco Tirado,
Hortensia Mecha:
Unified data path allocation and BIST intrusion.
Integration 28(1): 55-99 (1999) |
| 1998 |
| 5 |  | J. A. Maestro,
Daniel Mozos,
Hortensia Mecha:
A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process.
DATE 1998: 218-225 |
| 1997 |
| 4 |  | Hortensia Mecha,
Milagros Fernández:
Interconnection Delay and Clock Cycle Selection in High Level Synthesis.
VLSI Design 1997: 504-505 |
| 3 |  | R. Moreno,
Román Hermida,
Milagros Fernández,
Hortensia Mecha:
A unified approach for scheduling and allocation.
Integration 23(1): 1-35 (1997) |
| 1996 |
| 2 |  | Hortensia Mecha,
Milagros Fernández,
Francisco Tirado,
Julio Septién,
D. Motes,
Katzalin Olcoz:
A method for area estimation of data-path in high level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(2): 258-265 (1996) |
| 1994 |
| 1 |  | Hortensia Mecha,
Milagros Fernández,
Román Hermida,
Daniel Mozos,
Katzalin Olcoz:
Clock cycle estimation based on dead time and control unit area minimization.
Microprocessing and Microprogramming 40(10-12): 821-824 (1994) |