| 2008 |
|---|
| 202 | EE | David Atienza,
Giovanni De Micheli,
Luca Benini,
José L. Ayala,
Pablo Garcia Del Valle,
Michael DeBole,
Vijay Narayanan:
Reliability-aware design for nanometer-scale devices.
ASP-DAC 2008: 549-554 |
| 201 | EE | David Atienza,
Praveen Raghavan,
José Luis Ayala,
Giovanni De Micheli,
Francky Catthoor,
Diederik Verkest,
Marisa López-Vallejo:
Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures.
Integration 41(1): 38-48 (2008) |
| 200 | EE | David Atienza,
Federico Angiolini,
Srinivasan Murali,
Antonio Pullini,
Luca Benini,
Giovanni De Micheli:
Network-on-Chip design and synthesis outlook.
Integration 41(3): 340-359 (2008) |
| 2007 |
|---|
| 199 | EE | Salvatore Carta,
Andrea Acquaviva,
Pablo Garcia Del Valle,
David Atienza,
Giovanni De Micheli,
Fernando Rincón,
Luca Benini,
Jose Manuel Mendias:
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip.
ACM Great Lakes Symposium on VLSI 2007: 311-316 |
| 198 | EE | Srinivasan Murali,
Almir Mutapcic,
David Atienza,
Rajesh Gupta,
Stephen Boyd,
Giovanni De Micheli:
Temperature-aware processor frequency assignment for MPSoCs using convex optimization.
CODES+ISSS 2007: 111-116 |
| 197 | EE | Federico Angiolini,
M. Haykel Ben Jamaa,
David Atienza,
Luca Benini,
Giovanni De Micheli:
Interactive presentation: Improving the fault tolerance of nanometric PLA designs.
DATE 2007: 570-575 |
| 196 | EE | M. Haykel Ben Jamaa,
Kirsten E. Moselund,
David Atienza,
Didier Bouvet,
Adrian M. Ionescu,
Yusuf Leblebici,
Giovanni De Micheli:
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays.
ICCAD 2007: 765-772 |
| 195 | EE | Praveen Raghavan,
José L. Ayala,
David Atienza,
Francky Catthoor,
Giovanni De Micheli,
Marisa López-Vallejo:
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.
ISCAS 2007: 121-124 |
| 194 | EE | Giovanni De Micheli:
Design Technologies for Networks on Chips.
NOCS 2007: 149 |
| 193 | EE | Antonio Pullini,
Federico Angiolini,
Paolo Meloni,
David Atienza,
Srinivasan Murali,
Luigi Raffo,
Giovanni De Micheli,
Luca Benini:
NoC Design and Implementation in 65nm Technology.
NOCS 2007: 273-282 |
| 192 | EE | Abhishek Garg,
Ioannis Xenarios,
Luis Mendoza,
Giovanni De Micheli:
An Efficient Method for Dynamic Analysis of Gene Regulatory Networks and in silico Gene Perturbation Experiments.
RECOMB 2007: 62-76 |
| 191 | EE | Ilhan Hatirnaz,
Stéphane Badel,
Nuria Pazos,
Yusuf Leblebici,
Srinivasan Murali,
David Atienza,
Giovanni De Micheli:
Early wire characterization for predictable network-on-chip global interconnects.
SLIP 2007: 57-64 |
| 190 | EE | David Atienza,
Pablo Garcia Del Valle,
Giacomo Paci,
Francesco Poletti,
Luca Benini,
Giovanni De Micheli,
Jose Manuel Mendias,
Román Hermida:
HW-SW emulation framework for temperature-aware design in MPSoCs.
ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) |
| 189 | EE | Srinivasan Murali,
Giovanni De Micheli:
An Application-Specific Design Methodology for STbus Crossbar Generation
CoRR abs/0710.4671: (2007) |
| 188 | EE | Antonio Pullini,
Federico Angiolini,
Srinivasan Murali,
David Atienza,
Giovanni De Micheli,
Luca Benini:
Bringing NoCs to 65 nm.
IEEE Micro 27(5): 75-85 (2007) |
| 187 | EE | Tajana Simunic Rosing,
Kresimir Mihic,
Giovanni De Micheli:
Power and Reliability Management of SoCs.
IEEE Trans. VLSI Syst. 15(4): 391-403 (2007) |
| 186 | EE | Srinivasan Murali,
David Atienza,
Paolo Meloni,
Salvatore Carta,
Luca Benini,
Giovanni De Micheli,
Luigi Raffo:
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.
IEEE Trans. VLSI Syst. 15(8): 869-880 (2007) |
| 185 | EE | Srinivasan Murali,
Luca Benini,
Giovanni De Micheli:
An Application-Specific Design Methodology for On-Chip Crossbar Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1283-1296 (2007) |
| 184 | EE | Rutuparna Tamhankar,
Srinivasan Murali,
Stergios Stergiou,
Antonio Pullini,
Federico Angiolini,
Luca Benini,
Giovanni De Micheli:
Timing-Error-Tolerant Network-on-Chip Design Methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1297-1310 (2007) |
| 183 | EE | Sungroh Yoon,
Luca Benini,
Giovanni De Micheli:
Co-clustering: A Versatile Tool for Data Analysis in Biomedical Informatics.
IEEE Transactions on Information Technology in Biomedicine 11(4): 493-494 (2007) |
| 2006 |
|---|
| 182 | EE | Ayse Kivilcim Coskun,
Tajana Simunic Rosing,
Yusuf Leblebici,
Giovanni De Micheli:
A simulation methodology for reliability analysis in multi-core SoCs.
ACM Great Lakes Symposium on VLSI 2006: 95-99 |
| 181 | EE | Srinivasan Murali,
Martijn Coenen,
Andrei Radulescu,
Kees Goossens,
Giovanni De Micheli:
Mapping and configuration methods for multi-use-case networks on chips.
ASP-DAC 2006: 146-151 |
| 180 | EE | Elisa Ficarra,
Enrico Macii,
Giovanni De Micheli,
Luca Benini:
Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images.
CBMS 2006: 413-418 |
| 179 | EE | Martijn Coenen,
Srinivasan Murali,
Andrei Radulescu,
Kees Goossens,
Giovanni De Micheli:
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control.
CODES+ISSS 2006: 130-135 |
| 178 | EE | Igino Folcarelli,
Alex Susu,
Ties Kluter,
Giovanni De Micheli,
Andrea Acquaviva:
An opportunistic reconfiguration strategy for environmentally powered devices.
Conf. Computing Frontiers 2006: 171-176 |
| 177 | EE | David Atienza,
Pablo Garcia Del Valle,
Giacomo Paci,
Francesco Poletti,
Luca Benini,
Giovanni De Micheli,
Jose Manuel Mendias:
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip.
DAC 2006: 618-623 |
| 176 | EE | Srinivasan Murali,
David Atienza,
Luca Benini,
Giovanni De Micheli:
A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip.
DAC 2006: 845-848 |
| 175 | EE | Srinivasan Murali,
Martijn Coenen,
Andrei Radulescu,
Kees Goossens,
Giovanni De Micheli:
A methodology for mapping multiple use-cases onto networks on chips.
DATE 2006: 118-123 |
| 174 | EE | Srinivasan Murali,
Paolo Meloni,
Federico Angiolini,
David Atienza,
Salvatore Carta,
Luca Benini,
Giovanni De Micheli,
Luigi Raffo:
Designing application-specific networks on chips with floorplan information.
ICCAD 2006: 355-362 |
| 173 | EE | Federico Angiolini,
David Atienza,
Srinivasan Murali,
Luca Benini,
Giovanni De Micheli:
Reliability Support for On-Chip Memories Using Networks-on-Chip.
ICCD 2006 |
| 172 | EE | Christine Nardini,
Daniele Masotti,
Sungroh Yoon,
Enrico Macii,
Michael D. Kuo,
Giovanni De Micheli,
Luca Benini:
Mining Gene Sets for Measuring Similarities.
ISCC 2006: 227-232 |
| 171 | EE | David Atienza,
Praveen Raghavan,
José L. Ayala,
Giovanni De Micheli,
Francky Catthoor,
Diederik Verkest,
Marisa López-Vallejo:
Compiler-Driven Leakage Energy Reduction in Banked Register Files.
PATMOS 2006: 107-116 |
| 170 | EE | Giovanni De Micheli:
Nanoelectronics: Challenges and Opportunities.
PATMOS 2006: 658 |
| 169 | EE | Pablo Garcia Del Valle,
David Atienza,
Ivan Magan,
Javier Garcia Flores,
Esther Andres Perez,
Jose Manuel Mendias,
Luca Benini,
Giovanni De Micheli:
A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework.
VLSI-SoC 2006: 140-145 |
| 168 | EE | Srinivasan Murali,
Paolo Meloni,
Federico Angiolini,
David Atienza,
Salvatore Carta,
Luca Benini,
Giovanni De Micheli,
Luigi Raffo:
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.
VLSI-SoC 2006: 158-163 |
| 167 | EE | Sungroh Yoon,
Luca Benini,
Giovanni De Micheli:
A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(2): 358-377 (2006) |
| 166 | EE | Ayse Kivilcim Coskun,
Tajana Simunic,
Kresimir Mihic,
Giovanni De Micheli,
Yusuf Leblebici:
Analysis and Optimization of MPSoC Reliability.
J. Low Power Electronics 2(1): 56-69 (2006) |
| 2005 |
|---|
| 165 | EE | Srinivasan Murali,
Luca Benini,
Giovanni De Micheli:
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees.
ASP-DAC 2005: 27-32 |
| 164 | EE | Rutuparna Tamhankar,
Srinivasan Murali,
Giovanni De Micheli:
Performance driven reliable link design for networks on chips.
ASP-DAC 2005: 749-754 |
| 163 | EE | Srinivasan Murali,
Giovanni De Micheli:
An Application-Specific Design Methodology for STbus Crossbar Generation.
DATE 2005: 1176-1181 |
| 162 | EE | Stergios Stergiou,
Federico Angiolini,
Salvatore Carta,
Luigi Raffo,
Davide Bertozzi,
Giovanni De Micheli:
ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips.
DATE 2005: 1188-1193 |
| 161 | EE | Nicolas Genko,
David Atienza,
Giovanni De Micheli,
Jose Manuel Mendias,
Román Hermida,
Francky Catthoor:
A Complete Network-On-Chip Emulation Framework.
DATE 2005: 246-251 |
| 160 | EE | Sungroh Yoon,
Giovanni De Micheli:
Prediction of regulatory modules comprising microRNAs and target genes.
ECCB/JBI 2005: 100 |
| 159 | EE | Frederic Worm,
Paolo Ienne,
Patrick Thiran,
Giovanni De Micheli:
Self-calibrating networks-on-chip.
ISCAS (3) 2005: 2361-2364 |
| 158 | EE | Nicolas Genko,
David Atienza,
Giovanni De Micheli,
Luca Benini,
Jose Manuel Mendias,
Román Hermida,
Francky Catthoor:
A novel approach for network on chip emulation.
ISCAS (3) 2005: 2365-2368 |
| 157 | | Nicolas Genko,
David Atienza,
Giovanni De Micheli:
Exploration and Tuning of Custom NoC Topologies Using an FPGA-Based Framework.
PARCO 2005: 753-760 |
| 156 | EE | Tajana Simunic,
Kresimir Mihic,
Giovanni De Micheli:
Optimization of Reliability and Power Consumption in Systems on a Chip.
PATMOS 2005: 237-246 |
| 155 | | Davide Bertozzi,
Luca Benini,
Giovanni De Micheli:
Network On-Chip Design for Gigascale Systems-on-Chip.
The Industrial Information Technology Handbook 2005: 0- |
| 154 | EE | Giovanni De Micheli,
Al Dunlop:
IEEE Council for Electronic Design Automation: A new beginning.
IEEE Design & Test of Computers 22(4): 293-294 (2005) |
| 153 | EE | André Ivanov,
Giovanni De Micheli:
Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research.
IEEE Design & Test of Computers 22(5): 399-403 (2005) |
| 152 | EE | Partha Pratim Pande,
Cristian Grecu,
André Ivanov,
Resve A. Saleh,
Giovanni De Micheli:
Design, Synthesis, and Test of Networks on Chips.
IEEE Design & Test of Computers 22(5): 404-413 (2005) |
| 151 | EE | Srinivasan Murali,
Theo Theocharides,
Narayanan Vijaykrishnan,
Mary Jane Irwin,
Luca Benini,
Giovanni De Micheli:
Analysis of Error Recovery Schemes for Networks on Chips.
IEEE Design & Test of Computers 22(5): 434-442 (2005) |
| 150 | EE | Davide Bertozzi,
Antoine Jalabert,
Srinivasan Murali,
Rutuparna Tamhankar,
Stergios Stergiou,
Luca Benini,
Giovanni De Micheli:
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip.
IEEE Trans. Parallel Distrib. Syst. 16(2): 113-129 (2005) |
| 149 | EE | Frederic Worm,
Paolo Ienne,
Patrick Thiran,
Giovanni De Micheli:
A robust self-calibrating transmission scheme for on-chip networks.
IEEE Trans. VLSI Syst. 13(1): 126-139 (2005) |
| 148 | EE | Davide Bertozzi,
Luca Benini,
Giovanni De Micheli:
Error control schemes for on-chip communication links: the energy-reliability tradeoff.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 818-831 (2005) |
| 147 | EE | Sungroh Yoon,
Christine Nardini,
Luca Benini,
Giovanni De Micheli:
Discovering Coherent Biclusters from Gene Expression Data Using Zero-Suppressed Binary Decision Diagrams.
IEEE/ACM Trans. Comput. Biology Bioinform. 2(4): 339-354 (2005) |
| 2004 |
|---|
| 146 | EE | Sungroh Yoon,
Christine Nardini,
Luca Benini,
Giovanni De Micheli:
Enhanced pClustering and Its Applications to Gene Expression Data.
BIBE 2004: 275-282 |
| 145 | EE | Giovanni De Micheli:
Reliable communication in systems on chips.
DAC 2004: 77 |
| 144 | EE | Srinivasan Murali,
Giovanni De Micheli:
SUNMAP: a tool for automatic topology selection and generation for NoCs.
DAC 2004: 914-919 |
| 143 | EE | Antoine Jalabert,
Srinivasan Murali,
Luca Benini,
Giovanni De Micheli:
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip.
DATE 2004: 884-889 |
| 142 | EE | Srinivasan Murali,
Giovanni De Micheli:
Bandwidth-Constrained Mapping of Cores onto NoC Architectures.
DATE 2004: 896-903 |
| 141 | EE | Kresimir Mihic,
Tajana Simunic,
Giovanni De Micheli:
Reliability and Power Management of Integrated Systems.
DSD 2004: 5-11 |
| 140 | EE | Frederic Worm,
Paolo Ienne,
Patrick Thiran,
Giovanni De Micheli:
On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations.
IEEE Design & Test of Computers 21(6): 524-535 (2004) |
| 139 | EE | Terry Tao Ye,
Luca Benini,
Giovanni De Micheli:
Packetization and routing analysis of on-chip multiprocessor networks.
Journal of Systems Architecture 50(2-3): 81-104 (2004) |
| 2003 |
|---|
| 138 | EE | Armita Peymandoust,
Laura Pozzi,
Paolo Ienne,
Giovanni De Micheli:
Automatic Instruction Set Extension and Utilization for Embedded Processors.
ASAP 2003: 108- |
| 137 | EE | Terry Tao Ye,
Giovanni De Micheli:
Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics.
ASAP 2003: 97-107 |
| 136 | EE | Terry Tao Ye,
Luca Benini,
Giovanni De Micheli:
Packetized On-Chip Interconnect Communication Analysis for MPSoC.
DATE 2003: 10344-10349 |
| 135 | EE | Giovanni De Micheli:
Robust System Design with Uncertain Information.
MEMOCODE 2003: 283- |
| 134 | EE | Wajahat Qadeer,
Tajana Simunic Rosing,
John Ankcorn,
Venky Krishnan,
Giovanni De Micheli:
Heterogeneous Wireless Network Management.
PACS 2003: 86-100 |
| 133 | | Giovanni De Micheli:
CASS Brings Publishing to Its DAC Partnership.
IEEE Design & Test of Computers 20(3): 101-102 (2003) |
| 132 | EE | Armita Peymandoust,
Tajana Simunic,
Giovanni De Micheli:
Complex instruction and software library mapping for embedded software using symbolic algebra.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 964-975 (2003) |
| 131 | EE | Armita Peymandoust,
Giovanni De Micheli:
Application of symbolic computer algebra in high-level data-flow synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1154-1165 (2003) |
| 2002 |
|---|
| 130 | EE | Armita Peymandoust,
Giovanni De Micheli,
Tajana Simunic:
Complex library mapping for embedded software using symbolic algebra.
DAC 2002: 325-330 |
| 129 | EE | Terry Tao Ye,
Giovanni De Micheli,
Luca Benini:
Analysis of power consumption on switch fabrics in network routers.
DAC 2002: 524-529 |
| 128 | EE | Davide Bertozzi,
Luca Benini,
Giovanni De Micheli:
Low Power Error Resilient Encoding for On-Chip Data Buses.
DATE 2002: 102-109 |
| 127 | EE | Armita Peymandoust,
Tajana Simunic,
Giovanni De Micheli:
Low Power Embedded Software Optimization Using Symbolic Algebra.
DATE 2002: 1052-1058 |
| 126 | EE | Giovanni De Micheli,
Luca Benini:
Networks on Chip: A New Paradigm for Systems on Chip Design.
DATE 2002: 418-419 |
| 125 | EE | Terry Tao Ye,
Samit Chaudhuri,
F. Huang,
Hamid Savoj,
Giovanni De Micheli:
Physical synthesis for ASIC datapath circuits.
ISCAS (3) 2002: 365-368 |
| 124 | EE | Eui-Young Chung,
Giovanni De Micheli,
Luca Benini:
Contents provider-assisted dynamic voltage scaling for low energy multimedia applications.
ISLPED 2002: 42-47 |
| 123 | EE | Paolo Ienne,
Patrick Thiran,
Giovanni De Micheli,
Frederic Worm:
An Adaptive Low-Power Transmission Scheme for On-Chip Networks.
ISSS 2002: 92-100 |
| 122 | EE | Luca Benini,
Giovanni De Micheli:
Networks on Chips: A New SoC Paradigm.
IEEE Computer 35(1): 70-78 (2002) |
| 121 | EE | Eui-Young Chung,
Luca Benini,
Alessandro Bogliolo,
Yung-Hsiang Lu,
Giovanni De Micheli:
Dynamic Power Management for Nonstationary Service Requests.
IEEE Trans. Computers 51(11): 1345-1361 (2002) |
| 120 | EE | Yung-Hsiang Lu,
Luca Benini,
Giovanni De Micheli:
Power-aware operating systems for interactive systems.
IEEE Trans. VLSI Syst. 10(2): 119-134 (2002) |
| 119 | EE | Yung-Hsiang Lu,
Luca Benini,
Giovanni De Micheli:
Dynamic frequency scaling with buffer insertion for mixed workloads.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1284-1305 (2002) |
| 118 | EE | Eui-Young Chung,
Luca Benini,
Giovanni De Micheli,
Gabriele Luculli,
Marco Carilli:
Value-sensitive automatic code specialization for embedded software.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1051-1067 (2002) |
| 2001 |
|---|
| 117 | EE | Armita Peymandoust,
Giovanni De Micheli:
Using Symbolic Algebra in Algorithmic Level DSP Synthesis.
DAC 2001: 277-282 |
| 116 | EE | Tajana Simunic,
Luca Benini,
Andrea Acquaviva,
Peter W. Glynn,
Giovanni De Micheli:
Dynamic Voltage Scaling and Power Management for Portable Systems.
DAC 2001: 524-529 |
| 115 | EE | G. Martin,
Ralf Seepold,
Ting Zhang,
Luca Benini,
Giovanni De Micheli:
Component selection and matching for IP-based design.
DATE 2001: 40-46 |
| 114 | EE | Armita Peymandoust,
Giovanni De Micheli:
Symbolic Algebra and Timing Driven Data-flow Synthesis.
ICCAD 2001: 300-305 |
| 113 | EE | Eui-Young Chung,
Luca Benini,
Giovanni De Micheli:
Automatic source code specialization for energy reduction.
ISLPED 2001: 80-83 |
| 112 | | Preeti Ranjan Panda,
Luc Séméria,
Giovanni De Micheli:
Cache-efficient memory layout of aggregate data structures.
ISSS 2001: 101-106 |
| 111 | | Eui-Young Chung,
Luca Benini,
Giovanni De Micheli:
Source code transformation based on software cost analysis.
ISSS 2001: 153-158 |
| 110 | | Luca Benini,
Giovanni De Micheli:
Powering networks on chips.
ISSS 2001: 33-38 |
| 109 | EE | Yung-Hsiang Lu,
Giovanni De Micheli:
Comparing System-Level Power Management Policies.
IEEE Design & Test of Computers 18(2): 10-19 (2001) |
| 108 | EE | Tajana Simunic,
Luca Benini,
Giovanni De Micheli:
Energy-efficient design of battery-powered embedded systems.
IEEE Trans. VLSI Syst. 9(1): 15-28 (2001) |
| 107 | EE | Luc Séméria,
Koichi Sato,
Giovanni De Micheli:
Synthesis of hardware models in C with pointers and complex data structures.
IEEE Trans. VLSI Syst. 9(6): 743-756 (2001) |
| 106 | EE | Luc Séméria,
Giovanni De Micheli:
Resolution, optimization, and encoding of pointer variables for thebehavioral synthesis from C.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 213-233 (2001) |
| 105 | EE | Tajana Simunic,
Luca Benini,
Peter W. Glynn,
Giovanni De Micheli:
Event-driven power management.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 840-857 (2001) |
| 104 | EE | Luca Benini,
Giovanni De Micheli,
Antonio Lioy,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Synthesis of power-managed sequential components based oncomputational kernel extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1118-1131 (2001) |
| 2000 |
|---|
| 103 | EE | Yung-Hsiang Lu,
Luca Benini,
Giovanni De Micheli:
Low-power task scheduling for multiple devices.
CODES 2000: 39-43 |
| 102 | EE | Yung-Hsiang Lu,
Eui-Young Chung,
Tajana Simunic,
Giovanni De Micheli,
Luca Benini:
Quantitative Comparison of Power Management Algorithms.
DATE 2000: 20-26 |
| 101 | EE | Luc Séméria,
Koichi Sato,
Giovanni De Micheli:
Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C.
DATE 2000: 312-319 |
| 100 | EE | Tajana Simunic,
Luca Benini,
Peter W. Glynn,
Giovanni De Micheli:
Dynamic Power Management of Laptop Hard Disk.
DATE 2000: 736 |
| 99 | | Terry Tao Ye,
Giovanni De Micheli:
Data Path Placement with Regularity.
ICCAD 2000: 264-270 |
| 98 | EE | Giovanni De Micheli,
Tony Correale,
Pietro Erratico,
Srini Raghvendra,
Hugo De Man,
Jerry Frankil,
Vivek Tiwari:
Do our low-power tools have enough horse power? (panel session) (title only).
ISLPED 2000: 149 |
| 97 | EE | Yung-Hsiang Lu,
Luca Benini,
Giovanni De Micheli:
Operating-system directed power reduction.
ISLPED 2000: 37-42 |
| 96 | EE | Tajana Simunic,
Haris Vikalo,
Peter W. Glynn,
Giovanni De Micheli:
Energy efficient design of portable wireless systems.
ISLPED 2000: 49-54 |
| 95 | EE | Yung-Hsiang Lu,
Giovanni De Micheli,
Luca Benini:
Requester-Aware Power Reduction.
ISSS 2000: 18-24 |
| 94 | EE | Tajana Simunic,
Giovanni De Micheli,
Luca Benini,
Mat Hans:
Source Code Optimization and Profiling of Energy Consumption in Embedded Systems.
ISSS 2000: 193-199 |
| 93 | EE | Tajana Simunic,
Luca Benini,
Peter W. Glynn,
Giovanni De Micheli:
Dynamic power management for portable systems.
MOBICOM 2000: 11-19 |
| 92 | EE | Luca Benini,
Giovanni De Micheli:
System-level power optimization: techniques and tools.
ACM Trans. Design Autom. Electr. Syst. 5(2): 115-192 (2000) |
| 91 | EE | Luca Benini,
Giovanni De Micheli:
Synthesis of low-power selectively-clocked systems from high-level specification.
ACM Trans. Design Autom. Electr. Syst. 5(3): 311-321 (2000) |
| 90 | EE | Alessandro Bogliolo,
Luca Benini,
Giovanni De Micheli:
Regression-based RTL power modeling.
ACM Trans. Design Autom. Electr. Syst. 5(3): 337-372 (2000) |
| 89 | EE | Luca Benini,
Giovanni De Micheli,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Glitch power minimization by selective gate freezing.
IEEE Trans. VLSI Syst. 8(3): 287-298 (2000) |
| 88 | EE | Luca Benini,
Alessandro Bogliolo,
Giovanni De Micheli:
A survey of design techniques for system-level dynamic power management.
IEEE Trans. VLSI Syst. 8(3): 299-316 (2000) |
| 87 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
A multilevel engine for fast power simulation of realistic inputstreams.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 459-472 (2000) |
| 1999 |
|---|
| 86 | EE | Yung-Hsiang Lu,
Tajana Simunic,
Giovanni De Micheli:
Software controlled power management.
CODES 1999: 157-161 |
| 85 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms.
DAC 1999: 247-252 |
| 84 | EE | Tajana Simunic,
Luca Benini,
Giovanni De Micheli:
Cycle-Accurate Simulation of Energy Consumption in Embedded Systems.
DAC 1999: 867-872 |
| 83 | EE | Luca Benini,
Giovanni De Micheli,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Glitch Power Minimization by Gate Freezing.
DATE 1999: 163-167 |
| 82 | EE | James Smith,
Giovanni De Micheli:
Polynomial Methods for Allocating Complex Components.
DATE 1999: 217-222 |
| 81 | EE | Giovanni De Micheli:
Hardware Synthesis from C/C++ Models.
DATE 1999: 382-383 |
| 80 | EE | Eui-Young Chung,
Luca Benini,
Alessandro Bogliolo,
Giovanni De Micheli:
Dynamic Power Management for non-stationary service requests.
DATE 1999: 77-81 |
| 79 | EE | Yung-Hsiang Lu,
Giovanni De Micheli:
Adaptive Hard Disk Power Management on Personal Computers.
Great Lakes Symposium on VLSI 1999: 50- |
| 78 | EE | Eui-Young Chung,
Luca Benini,
Giovanni De Micheli:
Dynamic power management using adaptive learning tree.
ICCAD 1999: 274-279 |
| 77 | EE | Alessandro Bogliolo,
Luca Benini,
Bruno Riccò,
Giovanni De Micheli:
Efficient switching activity computation during high-level synthesis of control-dominated designs.
ISLPED 1999: 127-132 |
| 76 | EE | Tajana Simunic,
Luca Benini,
Giovanni De Micheli:
Energy-efficient design of battery-powered embedded systems.
ISLPED 1999: 212-217 |
| 75 | EE | Luca Benini,
Giovanni De Micheli:
System-level power optimization: techniques and tools.
ISLPED 1999: 288-293 |
| 74 | EE | Tajana Simunic,
Giovanni De Micheli,
Luca Benini:
Event-Driven Power Management of Portable Systems.
ISSS 1999: 18-23 |
| 73 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers.
ACM Trans. Design Autom. Electr. Syst. 4(4): 351-375 (1999) |
| 72 | | Luca Benini,
Giovanni De Micheli,
Antonio Lioy,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting.
IEEE Trans. Computers 48(8): 769-779 (1999) |
| 71 | EE | Luca Benini,
Alessandro Bogliolo,
Giuseppe A. Paleologo,
Giovanni De Micheli:
Policy optimization for dynamic power management.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 813-833 (1999) |
| 1998 |
|---|
| 70 | EE | James Smith,
Giovanni De Micheli:
Automated Composition of Hardware Components.
DAC 1998: 14-19 |
| 69 | EE | Giuseppe A. Paleologo,
Luca Benini,
Alessandro Bogliolo,
Giovanni De Micheli:
Policy Optimization for Dynamic Power Management.
DAC 1998: 182-187 |
| 68 | EE | Luca Benini,
Giovanni De Micheli,
Antonio Lioy,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Computational Kernels and their Application to Sequential Power Optimization.
DAC 1998: 764-769 |
| 67 | EE | Alessandro Bogliolo,
Luca Benini,
Giovanni De Micheli:
Characterization-Free Behavioral Power Modeling.
DATE 1998: 767-773 |
| 66 | EE | Luca Benini,
Giovanni De Micheli,
Donatella Sciuto,
Enrico Macii,
Cristina Silvano:
Address Bus Encoding Techniques for System-Level Power Optimization.
DATE 1998: 861- |
| 65 | EE | Diego C. Ruspini,
Oussama Khatib,
Giovanni De Micheli:
Hardware-Softw are Run-Time Systems and Robotics: A Case Study Vincent John Mooney III.
EUROMICRO 1998: 10162-10167 |
| 64 | EE | Marco Platzner,
Giovanni De Micheli:
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware.
FPL 1998: 69-78 |
| 63 | EE | Luca Benini,
Giovanni De Micheli,
Antonio Lioy,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Timed Supersetting and the Synthesis of Telescopic Units.
Great Lakes Symposium on VLSI 1998: 331-337 |
| 62 | EE | Luca Benini,
Giovanni De Micheli,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding.
Great Lakes Symposium on VLSI 1998: 8-12 |
| 61 | EE | Shin-ichi Minato,
Giovanni De Micheli:
Finding all simple disjunctive decompositions using irredundant sum-of-products forms.
ICCAD 1998: 111-117 |
| 60 | EE | Luc Séméria,
Giovanni De Micheli:
SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C.
ICCAD 1998: 340-346 |
| 59 | EE | James Smith,
Giovanni De Micheli:
Polynomial methods for component matching and verification.
ICCAD 1998: 678-685 |
| 58 | EE | Luca Benini,
Alessandro Bogliolo,
Giovanni De Micheli:
Dynamic power management of electronic systems.
ICCAD 1998: 696-702 |
| 57 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Stefano Quer:
Power optimization of core-based systems by address bus encoding.
IEEE Trans. VLSI Syst. 6(4): 554-562 (1998) |
| 56 | EE | Luca Benini,
Patrick Vuillod,
Giovanni De Micheli:
Iterative remapping for logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 948-964 (1998) |
| 55 | EE | Luca Benini,
Enrico Macii,
Massimo Poncino,
Giovanni De Micheli:
Telescopic units: a new paradigm for performance optimization of VLSI designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 220-232 (1998) |
| 1997 |
|---|
| 54 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Donatella Sciuto,
Cristina Silvano:
Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems.
Great Lakes Symposium on VLSI 1997: 77-82 |
| 53 | EE | Patrick Vuillod,
Luca Benini,
Giovanni De Micheli:
Generalized matching from theory to application.
ICCAD 1997: 13-20 |
| 52 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Fast power estimation for deterministic input streams.
ICCAD 1997: 494-501 |
| 51 | EE | Vincent John Mooney III,
Giovanni De Micheli:
Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system.
ICCAD 1997: 605-612 |
| 50 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Stefano Quer:
System-level power optimization of special purpose applications: the beach solution.
ISLPED 1997: 24-29 |
| 49 | EE | Patrick Vuillod,
Luca Benini,
Giovanni De Micheli:
Re-mapping for low power under tight timing constraints.
ISLPED 1997: 287-292 |
| 48 | EE | Luca Benini,
Giovanni De Micheli:
A survey of Boolean matching techniques for library binding.
ACM Trans. Design Autom. Electr. Syst. 2(3): 193-226 (1997) |
| 47 | EE | Alessandro Bogliolo,
Luca Benini,
Giovanni De Micheli,
Bruno Riccò:
Gate-level power and current simulation of CMOS integrated circuits.
IEEE Trans. VLSI Syst. 5(4): 473-488 (1997) |
| 46 | EE | Rajesh K. Gupta,
Giovanni De Micheli:
Specification and analysis of timing constraints for embedded systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 240-256 (1997) |
| 1996 |
|---|
| 45 | EE | Luca Benini,
Alessandro Bogliolo,
Giovanni De Micheli:
Distributed EDA Tool Integration: The PPP Paradigm.
ICCD 1996: 448-453 |
| 44 | EE | Alessandro Bogliolo,
Luca Benini,
Giovanni De Micheli,
Bruno Riccò:
Gate-level current waveform simulation of CMOS integrated circuits.
ISLPED 1996: 109-112 |
| 43 | EE | Patrick Vuillod,
Luca Benini,
Alessandro Bogliolo,
Giovanni De Micheli:
Clock skew optimization for peak current reduction.
ISLPED 1996: 265-270 |
| 42 | EE | Luca Benini,
Patrick Vuillod,
Claudionor José Nunes Coelho Jr.,
Giovanni De Micheli:
Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification.
ISSS 1996: 57- |
| 41 | EE | Jerry Chih-Yuan Yang,
Giovanni De Micheli,
Maurizio Damiani:
Scheduling and control generation with environmental constraints based on automata representations.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(2): 166-183 (1996) |
| 40 | EE | Luca Benini,
Giovanni De Micheli:
Automatic synthesis of low-power gated-clock finite-state machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(6): 630-643 (1996) |
| 39 | EE | Claudionor José Nunes Coelho Jr.,
Giovanni De Micheli:
Analysis and synthesis of concurrent digital circuits using control-flow expressions.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 854-876 (1996) |
| 1995 |
|---|
| 38 | EE | Luca Benini,
Giovanni De Micheli:
Transformation and synthesis of FSMs for low-power gated-clock implementation.
ISLPD 1995: 21-26 |
| 37 | EE | Maurizio Damiani,
Jerry Chih-Yuan Yang,
Giovanni De Micheli:
Optimization of combinational logic circuits based on compatible gates.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(11): 1316-1327 (1995) |
| 1994 |
|---|
| 36 | EE | Claudionor José Nunes Coelho Jr.,
Jerry Chih-Yuan Yang,
Vincent John Mooney III,
Giovanni De Micheli:
Redesigning hardware-software systems.
CODES 1994: 116-123 |
| 35 | EE | Rajesh K. Gupta,
Giovanni De Micheli:
Constrained software generation for hardware-software systems.
CODES 1994: 56-63 |
| 34 | | Jerry Chih-Yuan Yang,
Giovanni De Micheli,
Maurizio Damiani:
Scheduling with Environmental Constraints based on Automata Representations.
EDAC-ETC-EUROASIC 1994: 495-501 |
| 33 | EE | Claudionor José Nunes Coelho Jr.,
Giovanni De Micheli:
Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints.
ICCAD 1994: 175-181 |
| 32 | EE | Polly Siegel,
Giovanni De Micheli:
Decomposition methods for library binding of speed-independent asynchronous designs.
ICCAD 1994: 558-565 |
| 31 | | Jérôme Fron,
Jerry Chih-Yuan Yang,
Maurizio Damiani,
Giovanni De Micheli:
A Synthesis Framework Based on Trace and Automata Theory.
ISCAS 1994: 291-294 |
| 30 | | Rajesh K. Gupta,
Claudionor José Nunes Coelho Jr.,
Giovanni De Micheli:
Program Implementation Schemes for Hardware-Software Systems.
IEEE Computer 27(1): 48-55 (1994) |
| 29 | EE | Luca Benini,
Polly Siegel,
Giovanni De Micheli:
Saving Power by Synthesizing Gated Clocks for Sequential Circuits.
IEEE Design & Test of Computers 11(4): 32-41 (1994) |
| 1993 |
|---|
| 28 | EE | Polly Siegel,
Giovanni De Micheli,
David L. Dill:
Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs.
DAC 1993: 61-67 |
| 27 | EE | Maurizio Damiani,
Jerry Chih-Yuan Yang,
Giovanni De Micheli:
Optimization of Combinational Logic Circuits Based on Compatible Gates.
DAC 1993: 631-636 |
| 26 | EE | Jerry R. Burch,
David L. Dill,
Elizabeth Wolf,
Giovanni De Micheli:
Modeling hierarchical combinational circuits.
ICCAD 1993: 612-617 |
| 25 | | Giovanni De Micheli:
High-Level Synthesis of Digital Circuits.
Advances in Computers 37: 207-283 (1993) |
| 24 | EE | Rajesh K. Gupta,
Giovanni De Micheli:
Hardware-Software Cosynthesis for Digital Systems.
IEEE Design & Test of Computers 10(3): 29-41 (1993) |
| 23 | EE | Dave Filo,
David C. Ku,
Claudionor José Nunes Coelho Jr.,
Giovanni De Micheli:
Interface optimization for concurrent systems under timing constraints.
IEEE Trans. VLSI Syst. 1(3): 268-281 (1993) |
| 22 | EE | Derek C. Wong,
Giovanni De Micheli,
Michael J. Flynn:
Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 25-46 (1993) |
| 21 | EE | Maurizio Damiani,
Giovanni De Micheli:
Don't care set specifications in combinational and synchronous logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(3): 365-388 (1993) |
| 20 | EE | Frederic Mailhot,
Giovanni De Micheli:
Algorithms for technology mapping based on binary decision diagrams and on Boolean operations.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 599-620 (1993) |
| 1992 |
|---|
| 19 | EE | Rajesh K. Gupta,
Claudionor José Nunes Coelho Jr.,
Giovanni De Micheli:
Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components.
DAC 1992: 225-230 |
| 18 | EE | Maurizio Damiani,
Giovanni De Micheli:
Recurrence Equations and the Optimization of Synchronous Logic Circuits.
DAC 1992: 556-561 |
| 17 | EE | David C. Ku,
Giovanni De Micheli:
Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 696-718 (1992) |
| 1991 |
|---|
| 16 | EE | Silvia Ercolani,
Giovanni De Micheli:
Technology Mapping for Electrically Programmable Gate Arrays.
DAC 1991: 234-239 |
| 15 | EE | David C. Ku,
Dave Filo,
Giovanni De Micheli:
Control Optimization Based on Resynchronization of Operations.
DAC 1991: 366-371 |
| 14 | EE | Giovanni De Micheli:
Synchronous logic synthesis: algorithms for cycle-time minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 63-73 (1991) |
| 1990 |
|---|
| 13 | EE | David C. Ku,
Giovanni De Micheli:
Relative Scheduling Under Timing Constraints.
DAC 1990: 59-64 |
| 12 | | Rajesh K. Gupta,
Giovanni De Micheli:
Partitioning of Functional Models of Synchronous Digital Systems.
ICCAD 1990: 216-219 |
| 11 | | Maurizio Damiani,
Giovanni De Micheli:
Observability Don't Care Sets and Boolean Relations.
ICCAD 1990: 502-505 |
| 10 | EE | Giovanni De Micheli,
David C. Ku,
Frederic Mailhot,
Thomas K. Truong:
The Olympus Synthesis System.
IEEE Design & Test of Computers 7(5): 37-53 (1990) |
| 9 | | Giovanni De Micheli:
Guest Editorial: High-Level Synthesis of Digital Circuits.
IEEE Design & Test of Computers 7(5): 6-7 (1990) |
| 1988 |
|---|
| 8 | EE | Giovanni De Micheli,
David C. Ku:
HERCULES - a System for High-Level Synthesis.
DAC 1988: 483-488 |
| 1987 |
|---|
| 7 | EE | Giovanni De Micheli:
Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 751-765 (1987) |
| 1986 |
|---|
| 6 | EE | Giovanni De Micheli,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Correction to "Optimal State Assignment for Finite State Machines".
IEEE Trans. on CAD of Integrated Circuits and Systems 5(1): 239-239 (1986) |
| 5 | EE | Giovanni De Micheli:
Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 597-616 (1986) |
| 1985 |
|---|
| 4 | EE | Giovanni De Micheli,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Optimal State Assignment for Finite State Machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 269-285 (1985) |
| 1984 |
|---|
| 3 | EE | Giovanni De Micheli,
Alberto L. Sangiovanni-Vincentelli:
Correction to "Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications".
IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 256-256 (1984) |
| 1983 |
|---|
| 2 | EE | Giovanni De Micheli,
Alberto L. Sangiovanni-Vincentelli:
Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 2(3): 151-167 (1983) |
| 1 | EE | Giovanni De Micheli,
A. Richard Newton,
Alberto L. Sangiovanni-Vincentelli:
Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 2(3): 167-180 (1983) |
