Linda S. Milor

Linda Milor

	2009
17		Muhammad Bashir, Linda Milor: Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements. IEEE Design & Test of Computers 26(6): 18-27 (2009)
16		Seyed-Abdollah Aftabjahani, Linda S. Milor: Timing analysis with compact variation-aware standard cell models. Integration 42(3): 312-320 (2009)
	2008
15		Seyed-Abdollah Aftabjahani, Linda S. Milor: Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis. ISQED 2008: 148-151
14		Cheng Jia, Linda S. Milor: A BIST Circuit for DLL Fault Detection. IEEE Trans. VLSI Syst. 16(12): 1687-1695 (2008)
13		Munkang Choi, Linda S. Milor: Diagnosis of Optical Lithography Faults With Product Test Sets. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1657-1669 (2008)
	2006
12		Munkang Choi, Linda S. Milor: Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1350-1367 (2006)
	2005
11		Changsoo Hong, Linda S. Milor, Munkang Choi, Tom Lin: Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models. Microelectronics Reliability 45(9-11): 1305-1310 (2005)
	2003
10		Cheng Jia, Linda S. Milor: A BIST Solution for The Test of I/O Speed. ITC 2003: 1023-1030
	2002
9		Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu: Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 544-553 (2002)
	2000
8		Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu: Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. ICCAD 2000: 62-67
	1996
7		Mien Li, Linda S. Milor: Computing Parametric Yield Adaptively Using Local Linear Models. DAC 1996: 831-836
6		Bozena Kaminska, Tad A. Kwasniewski, Linda S. Milor, G. Roberts, P. Flahive, Jérôme Wojcik: Is High Frequency Analog DFT Possible? VTS 1996: 214-215
	1994
5		Linda S. Milor, Alberto L. Sangiovanni-Vincentelli: Minimizing production test time to detect faults in analog circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 796-813 (1994)
	1990
4		Linda Milor, Alberto L. Sangiovanni-Vincentelli: Computing Parametric Yield Accurately and Efficiently. ICCAD 1990: 116-119
3		Linda Milor, Alberto L. Sangiovanni-Vincentelli: Optimal Test Set Design for Analog Circuits. ICCAD 1990: 294-297
	1989
2		Linda S. Milor, V. Visvanathan: Detection of catastrophic faults in analog integrated circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 8(2): 114-130 (1989)
	1986
1		V. Visvanathan, Linda S. Milor: An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation. Symposium on Computational Geometry 1986: 207-215

Coauthor Index

1	Seyed-Abdollah Aftabjahani	[15] [16]
2	Muhammad Bashir	[17]
3	Pinhong Chen	[8] [9]
4	Munkang Choi	[11] [12] [13]
5	P. Flahive	[6]
6	Changsoo Hong	[11]
7	Chenming Hu	[8] [9]
8	Cheng Jia	[10] [14]
9	Bozena Kaminska	[6]
10	Kurt Keutzer	[8] [9]
11	Tad A. Kwasniewski	[6]
12	Mien Li	[7]
13	Tom Lin	[11]
14	Michael Orshansky	[8] [9]
15	G. Roberts	[6]
16	Alberto L. Sangiovanni-Vincentelli	[3] [4] [5]
17	V. Visvanathan	[1] [2]
18	Jérôme Wojcik	[6]

Colors in the list of coauthors