 | 2007 |
|---|
| 7 |       | Naghmeh Karimi,
Shahrzad Mirkhani,
Zainalabedin Navabi,
Fabrizio Lombardi:
RT level reliability enhancement by constructing dynamic TMRS.
ACM Great Lakes Symposium on VLSI 2007: 172-175 |
| 6 | | Parisa Razaghi,
Shahrzad Mirkhani,
Zainalabedin Navabi:
A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library.
FDL 2007: 171-176 |
| 2005 |
|---|
| 5 | | Shahrzad Mirkhani,
Zainalabedin Navabi:
Enhancing Fault Simulation Performance by Dynamic Fault Clustering.
Asian Test Symposium 2005: 278-283 |
| 2004 |
|---|
| 4 | | Zainalabedin Navabi,
Shahrzad Mirkhani,
Meisam Lavasani,
Fabrizio Lombardi:
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation.
J. Electronic Testing 20(6): 575-589 (2004) |
| 2002 |
|---|
| 3 | | Shahrzad Mirkhani,
Meisam Lavasani,
Zainalabedin Navabi:
Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models.
Asian Test Symposium 2002: 374- |
| 2001 |
|---|
| 2 | | Hamed Farshbaf,
Mina Zolfy,
Shahrzad Mirkhani,
Zainalabedin Navabi:
Fault Simulation for VHDL Based Test Bench and BIST Evaluation.
Asian Test Symposium 2001: 396- |
| 1 | | Mina Zolfy,
Shahrzad Mirkhani,
Zainalabedin Navabi:
Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation.
DATE 2001: 823 |
