Prabhat Mishra

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2008
32EEMingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita: Coverage-driven automatic test generation for uml activity diagrams. ACM Great Lakes Symposium on VLSI 2008: 139-142
31EEKanad Basu, Prabhat Mishra: A novel test-data compression technique using application-aware bitmask and dictionary selection methods. ACM Great Lakes Symposium on VLSI 2008: 83-88
30EESeok-Won Seong, Prabhat Mishra: Bitmask-Based Code Compression for Embedded Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 673-685 (2008)
2007
29EEXianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra, Xu Cheng: A Retargetable Software Timing Analyzer Using Architecture Description Language. ASP-DAC 2007: 396-401
28EESeok-Won Seong, Prabhat Mishra: An efficient code compression technique using application-aware bitmask and dictionary selection methods. DATE 2007: 582-587
2006
27EEHeon-Mo Koo, Prabhat Mishra: Test generation using SAT-based bounded model checking for validation of pipelined processors. ACM Great Lakes Symposium on VLSI 2006: 362-365
26EEHeon-Mo Koo, Prabhat Mishra: Functional test generation using property decompositions for validation of pipelined processors. DATE 2006: 1240-1245
25EESeok-Won Seong, Prabhat Mishra: A bitmask-based code compression technique for embedded systems. ICCAD 2006: 251-254
24EEHeon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir: Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. MTV 2006: 33-36
23EEPrabhat Mishra, Aviral Shrivastava, Nikil Dutt: Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. ACM Trans. Design Autom. Electr. Syst. 11(3): 626-658 (2006)
22EEMehrdad Reshadi, Nikil Dutt, Prabhat Mishra: A retargetable framework for instruction-set architecture simulation. ACM Trans. Embedded Comput. Syst. 5(2): 431-452 (2006)
2005
21EEMehrdad Reshadi, Prabhat Mishra: Memory access optimizations in instruction-set simulators. CODES+ISSS 2005: 237-242
20EEPrabhat Mishra, Nikil D. Dutt: Functional Coverage Driven Test Generation for Validation of Pipelined Processors. DATE 2005: 678-683
19EEPrabhat Mishra, Heon-Mo Koo, Zhuo Huang: Language-driven Validation of Pipelined Processors using Satisfiability Solvers. MTV 2005: 119-126
18EEPrabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A methodology for validation of microprocessors using symbolic simulation. IJES 1(1/2): 14-22 (2005)
2004
17EEPrabhat Mishra, Nikil Dutt: Graph-Based Functional Test Program Generation for Pipelined Processors. DATE 2004: 182-187
16EEPrabhat Mishra, Nikil D. Dutt: Functional Validation of Programmable Architectures. DSD 2004: 12-19
15EEPrabhat Mishra, Nikil D. Dutt, Yaron Kashai: Functional Verification of Pipelined Processors: A Case Study. MTV 2004: 79-84
14EEPrabhat Mishra, Arun Kejariwal, Nikil Dutt: Synthesis-driven Exploration of Pipelined Embedded Processors. VLSI Design 2004: 921-926
13EEPrabhat Mishra, Nikil Dutt: Modeling and validation of pipeline specifications. ACM Trans. Embedded Comput. Syst. 3(1): 114-139 (2004)
12EEPrabhat Mishra, Mahesh Mamidipaka, Nikil Dutt: Processor-memory coexploration using an architecture description language. ACM Trans. Embedded Comput. Syst. 3(1): 140-162 (2004)
11EEPrabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A Top-Down Methodology for Microprocessor Validation. IEEE Design & Test of Computers 21(2): 122-131 (2004)
2003
10EEMehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, Nikil D. Dutt: An efficient retargetable framework for instruction-set simulation. CODES+ISSS 2003: 13-18
9EEMehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt: Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. DAC 2003: 758-763
8EEPrabhat Mishra, Arun Kejariwal, Nikil Dutt: Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models. IEEE International Workshop on Rapid System Prototyping 2003: 226-232
7EEPrabhat Mishra, Nikil D. Dutt: A Methodology for Validation of Microprocessors using Equivalence Checking. MTV 2003: 83-88
2002
6EEPrabhat Mishra, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama: Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language. ASP-DAC 2002: 458-466
5EEPrabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama: Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. DATE 2002: 36-43
4 Prabhat Mishra, Nikil D. Dutt: Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions. DIPES 2002: 81-90
3EEPrabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. VLSI Design 2002: 458-
2001
2 Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau: Functional abstraction driven design space exploration of heterogeneous programmable architectures. ISSS 2001: 256-261
1EEPrabhat Mishra, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. VLSI Design 2001: 70-75

Coauthor Index

1Magdy S. Abadir [11] [18] [24]
2Nikhil Bansal [10]
3Kanad Basu [31]
4Jayanta Bhadra [24]
5Mingsong Chen [32]
6Xu Cheng [29]
7Nikil D. Dutt (Nikil Dutt) [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [20] [22] [23]
8Peter Grun [1] [3] [6]
9Ashok Halambi [3] [6]
10Zhuo Huang [19]
11Dhrubajyoti Kalita [32]
12Yaron Kashai [15]
13Arun Kejariwal [8] [14]
14Heon-Mo Koo [19] [24] [26] [27]
15Narayanan Krishnamurthy [11] [18]
16Xianfeng Li [29]
17Mahesh Mamidipaka [12]
18Tulika Mitra [29]
19Alexandru Nicolau (Alex Nicolau) [1] [2] [3] [5] [6]
20Mehrdad Reshadi [9] [10] [21] [22]
21Abhik Roychoudhury [29]
22Seok-Won Seong [25] [28] [30]
23Aviral Shrivastava [23]
24Hiroyuki Tomiyama [3] [5] [6]

Colors in the list of coauthors

Copyright © Wed Jul 23 13:04:14 2008 by Michael Ley (ley@uni-trier.de)