 | 2009 |
| 10 |  | Hiroshi Fuketa,
Masanori Hashimoto,
Yukio Mitsuyama,
Takao Onoye:
Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction.
ASP-DAC 2009: 266-271 |
| 9 |  | Koichi Hamamoto,
Masanori Hashimoto,
Yukio Mitsuyama,
Takao Onoye:
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits.
ISLPED 2009: 51-56 |
| 8 |  | Koichi Hamamoto,
Hiroshi Fuketa,
Masanori Hashimoto,
Yukio Mitsuyama,
Takao Onoye:
An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability.
IEICE Transactions 92-C(2): 281-285 (2009) |
| 2008 |
| 7 |  | Koichi Hamamoto,
Hiroshi Fuketa,
Masanori Hashimoto,
Yukio Mitsuyama,
Takao Onoye:
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --.
ACM Great Lakes Symposium on VLSI 2008: 387-390 |
| 6 |  | Hiroshi Fuketa,
Masanori Hashimoto,
Yukio Mitsuyama,
Takao Onoye:
Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits.
ISLPED 2008: 3-8 |
| 5 |  | Yukio Mitsuyama,
Kazuma Takahashi,
Rintaro Imai,
Masanori Hashimoto,
Takao Onoye,
Isao Shirakawa:
Area-Efficient Reconfigurable Architecture for Media Processing.
IEICE Transactions 91-A(12): 3651-3662 (2008) |
| 2005 |
| 4 |  | Yukio Mitsuyama,
Motoki Kimura,
Takao Onoye,
Isao Shirakawa:
Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems.
IEICE Transactions 88-A(4): 899-906 (2005) |
| 2001 |
| 3 |  | Yukio Mitsuyama,
Zaldy Andales,
Takao Onoye,
Isao Shirakawa:
A dynamically reconfigurable hardware-based cipher chip.
ASP-DAC 2001: 11-12 |
| 2 |  | Yukio Mitsuyama,
Zaldy Andales,
Takao Onoye,
Isao Shirakawa:
VLSI architecture of dynamically reconfigurable hardware-based cipher.
ISCAS (4) 2001: 734-737 |
| 1999 |
| 1 |  | Koji Asari,
Yukio Mitsuyama,
Takao Onoye,
Isao Shirakawa,
Hiroshige Hirano,
Toshiyuki Honda,
Tatsuo Otsuki,
Takaaki Baba,
Teresa H. Y. Meng:
FeRAM Circuit Technology for System on a Chip.
Evolvable Hardware 1999: 193- |