Junichi Miyakoshi Coauthor index DBLP Vis pubzone.org

List of publications from the DBLP Bibliography Server - FAQ
Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo

DBLP keys2008
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYuichiro Murachi, Kusuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto: A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding. ISCAS 2008: 848-851
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. IEEE Trans. VLSI Syst. 16(6): 620-627 (2008)
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Masahiko Yoshimoto: A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition. IEICE Transactions 91-C(4): 457-464 (2008)
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYuichiro Murachi, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto: A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer. IEICE Transactions 91-C(4): 465-478 (2008)
2006
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED 2006: 61-66
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJunichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno: A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. VLSI-SoC 2006: 192-197
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJunichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto: A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture. IEICE Transactions 89-A(12): 3623-3633 (2006)
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Transactions 89-A(12): 3634-3641 (2006)
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJunichi Miyakoshi, Yuichiro Murachi, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto: A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing. IEICE Transactions 89-C(11): 1629-1636 (2006)
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNoriyuki Minegishi, Junichi Miyakoshi, Yuki Kuroda, Tadayoshi Katagiri, Yuki Fukuyama, Ryo Yamamoto, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto: VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation. IEICE Transactions 89-C(3): 230-242 (2006)
2005
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Junichi Miyakoshi, Masayuki Miyama, Masahiko Yoshimoto: A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application. IEICE Transactions 88-A(12): 3492-3499 (2005)
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJunichi Miyakoshi, Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Masayuki Miyama, Masahiko Yoshimoto: A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation. IEICE Transactions 88-C(4): 559-569 (2005)
2004
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYuki Kuroda, Junichi Miyakoshi, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto: A sub-mW MPEG-4 motion estimation processor core for mobile video application. ASP-DAC 2004: 527-528

Coauthor Index

1Hidehiro Fujiwara [6] [9] [12]
2Yuki Fukuyama [4] [11]
3Masaki Hamamoto [7] [8] [10] [13]
4Koji Hamano [2] [3]
5Hideo Hashimoto [1] [4]
6Takahiro Iinuma [7] [8] [10] [13]
7Kousuke Imamura [1] [4]
8Hajime Ishihara [11]
9Tomokazu Ishihara [5] [7] [8] [10] [13]
10Tetsuya Kamino [13]
11Tadayoshi Katagiri [4]
12Hiroshi Kawaguchi [5] [6] [7] [8] [9] [10] [11] [12] [13]
13Kentaro Kawakami [6]
14Yuki Kuroda [1] [4]
15Jangchung Lee [10] [13]
16Yoshio Matsuda [11]
17Tetsuro Matsuno [2] [3] [7] [8]
18Shinji Mikami [6]
19Noriyuki Minegishi [4]
20Masayuki Miyama [1] [2] [3] [4] [7] [11]
21Kusuke Mizuno [13]
22Yasuhiro Morita [6] [9] [12]
23Yuichiro Murachi [2] [3] [5] [7] [8] [9] [10] [11] [12] [13]
24Koji Nii [6] [9] [12]
25Hiroki Noguchi [6] [12]
26Ryo Yamamoto [4] [11]
27Fang Yin [10] [13]
28Masahiko Yoshimoto [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]

Copyright © Sat Nov 28 20:06:51 2009 by Michael Ley (ley@uni-trier.de)