Yoshikazu Miyanaga

	2008
28		Shingo Yoshizawa, Kazuto Nishi, Yoshikazu Miyanaga: Reconfigurable two-dimensional pipeline FFT processor in OFDM cognitive radio systems. ISCAS 2008: 1248-1251
27		Shingo Yoshizawa, Yasushi Yamauchi, Yoshikazu Miyanaga: A complete pipelined MMSE detection architecture in a 4x4 MIMO-OFDM receiver. ISCAS 2008: 2486-2489
26		Rhandley D. Cajote, Supavadee Aramvith, Rowena Cristina L. Guevara, Yoshikazu Miyanaga: FMO slice group maps using spatial and temporal indicators for H.264 wireless video transmission. ISCAS 2008: 3566-3569
25		Chusit Pradabpet, Shingo Yoshizawa, Yoshikazu Miyanaga, Kobchai Dejhan: New PAPR Reduction in OFDM System Using Hybrid of PTS-APPR Methods with Coded Side Information Technique. IEICE Transactions 91-A(10): 2973-2979 (2008)
24		Xin Xu, Noboru Hayasaka, Yoshikazu Miyanaga: Robust Speech Spectra Restoration against Unspecific Noise Conditions for Pitch Detection. IEICE Transactions 91-A(3): 775-781 (2008)
23		Shingo Yoshizawa, Yasushi Yamauchi, Yoshikazu Miyanaga: VLSI Implementation of a Complete Pipeline MMSE Detector for a 4 x 4 MIMO-OFDM Receiver. IEICE Transactions 91-A(7): 1757-1762 (2008)
	2007
22		Takayuki Sugawara, Shingo Yoshizawa, Yoshikazu Miyanaga: Dynamic Reconfigurable Architecture for a Low-Power Despreader in VSF-OFCDM Systems. ISCAS 2007: 2287-2290
21		Shingo Yoshizawa, Yoshikazu Miyanaga: Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation. ISCAS 2007: 3175-3178
	2006
20		Shingo Yoshizawa, Yoshikazu Miyanaga: VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System. APCCAS 2006: 93-96
19		Shingo Yoshizawa, Yoshikazu Miyanaga, H. Ochi, Y. Itoh, N. Hataoka, B. Sai, N. Takayama, M. Hirata: 300-Mbps OFDM baseband transceiver for wireless LAN systems. ISCAS 2006
18		Naoya Wada, Noboru Hayasaka, Shingo Yoshizawa, Yoshikazu Miyanaga: Direct control on modulation spectrum for noise-robust speech recognition and spectral subtraction. ISCAS 2006
17		Noboru Hayasaka, Yoshikazu Miyanaga: Spectrum filtering with FRM for robust speech recognition. ISCAS 2006
16		Shingo Yoshizawa, Yoshikazu Miyanaga: Tunable word length architecture for low power wireless OFDM demodulator. ISCAS 2006
15		Shingo Yoshizawa, Yoshikazu Miyanaga: Tunable Wordlength Architecture for a Low Power Wireless OFDM Demodulator. IEICE Transactions 89-A(10): 2866-2873 (2006)
14		Kazuma Fujioka, Noboru Hayasaka, Yoshikazu Miyanaga, Norinobu Yoshida: Noise reduction of speech signals by running spectrum filtering. Systems and Computers in Japan 37(14): 52-61 (2006)
	2005
13		Yasuyuki Hatakawa, Shingo Yoshizawa, Yoshikazu Miyanaga: Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder. ISCAS (1) 2005: 25-28
12		Qi Zhu, Noriyuki Ohtsuki, Yoshikazu Miyanaga, Norinobu Yoshida: Noise-Robust Speech Analysis Using Running Spectrum Filtering. IEICE Transactions 88-A(2): 541-548 (2005)
	2004
11		Shingo Yoshizawa, Naoya Wada, Noboru Hayasaka, Yoshikazu Miyanaga: Scalable architecture for word HMM-based speech recognition. ISCAS (3) 2004: 417-420
	2002
10		Takayuki Sugawara, Yoshikazu Miyanaga, Norinobu Yoshida: A Design of Analog C-Matrix Circuits Used for Signal/Data Processing. VLSI Design 2002: 355-359
	1999
9		H. Ryu, Yoshikazu Miyanaga, Koji Tochinai: An image compression using self-organization with genetic algorithm. ISCAS (4) 1999: 5-8
	1997
8		Hiroshi Echizen-ya, Kenji Araki, Yoshikazu Miyanaga, Koji Tochinai: An Improvement in the Selection Process of Machine Translation Using Inductive Learning with Genetic Algorithms. ANLP 1997: 11-12
	1995
7		Honglan Jin, Yoshikazu Miyanaga, Koji Tochinai: Design of a Compact Cluster Structure by Using Genetic Algorithms. ISCAS 1995: 1512-1515
6		Rafiqul Islam, Makoto Hiroshige, Yoshikazu Miyanaga, Koji Tochinai: Phoneme Recognition System Based on a Modified TDNN Using Self-Organizing Clustering Network. ISCAS 1995: 1816-1819
5		Yoshikazu Miyanaga, Honglan Jin, Rafiqul Islam, Koji Tochinai: A Self-Organized Network with a Supervised Training. ISCAS 1995: 482-485
	1994
4		Jun'ya Shimizu, Yoshikazu Miyanaga, Koji Tochinai: An Estimation of Time-Varying Parameters using Multi-AR Lattice Models in Subbands. ISCAS 1994: 245-248
	1993
3		Frederico Buchholz Maciel, Yoshikazu Miyanaga, Koji Tochinai: A Performance-driven Approach to the High-level Synthesis of DSP Algorithms. ISCAS 1993: 1658-1661
2		Yoshikazu Miyanaga, Takeshi Nagae, Tateo Shimozawa, Koji Tochinai: Neuron architecture based on jamming avoidance response of an electric fish. ISCAS 1993: 2600-2603
1		Frederico Buchholz Maciel, Yoshikazu Miyanaga, Koji Tochinai: An optimization technique for lowering the iteration bound of DSP programs. VLSI Signal Processing 5(2-3): 273-282 (1993)

Coauthor Index

1	Kenji Araki	[8]
2	Supavadee Aramvith	[26]
3	Rhandley D. Cajote	[26]
4	Kobchai Dejhan	[25]
5	Hiroshi Echizen-ya	[8]
6	Kazuma Fujioka	[14]
7	Rowena Cristina L. Guevara	[26]
8	Yasuyuki Hatakawa	[13]
9	N. Hataoka	[19]
10	Noboru Hayasaka	[11] [14] [17] [18] [24]
11	M. Hirata	[19]
12	Makoto Hiroshige	[6]
13	Rafiqul Islam	[5] [6]
14	Y. Itoh	[19]
15	Honglan Jin	[5] [7]
16	Frederico Buchholz Maciel	[1] [3]
17	Takeshi Nagae	[2]
18	Kazuto Nishi	[28]
19	H. Ochi	[19]
20	Noriyuki Ohtsuki	[12]
21	Chusit Pradabpet	[25]
22	H. Ryu	[9]
23	B. Sai	[19]
24	Jun'ya Shimizu	[4]
25	Tateo Shimozawa	[2]
26	Takayuki Sugawara	[10] [22]
27	N. Takayama	[19]
28	Koji Tochinai	[1] [2] [3] [4] [5] [6] [7] [8] [9]
29	Naoya Wada	[11] [18]
30	Xin Xu	[24]
31	Yasushi Yamauchi	[23] [27]
32	Norinobu Yoshida	[10] [12] [14]
33	Shingo Yoshizawa	[11] [13] [15] [16] [18] [19] [20] [21] [22] [23] [25] [27] [28]
34	Qi Zhu	[12]

Colors in the list of coauthors