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12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto: Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL 2007: 43
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAkira Mochizuki, Masatomo Miura, Takahiro Hanyu: High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction. ISMVL 2007: 57
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAkira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu: Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry. IEICE Transactions 90-C(4): 683-691 (2007)
2006
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAkira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu: Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits. ISMVL 2006: 14
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAkira Mochizuki, Takahiro Hanyu: Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic. ISMVL 2006: 5
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAkira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu: Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic. IEICE Transactions 89-C(11): 1591-1597 (2006)
2005
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNaoya Onizawa, Akira Mochizuki, Takahiro Hanyu: Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders. ISMVL 2005: 138-143
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAkira Mochizuki, Hiromitsu Kimura, Mitsuru Ibuki, Takahiro Hanyu: TMR-Based Logic-in-Memory Circuit for Low-Power VLSI. IEICE Transactions 88-A(6): 1408-1415 (2005)
2004
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAkira Mochizuki, Takashi Takeuchi, Takahiro Hanyu: Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding. ISMVL 2004: 192-197
2003
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTakahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Dynamic Source-Coupled Logic. ISMVL 2003: 207-212
1995
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTakahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. ISMVL 1995: 64-
1994
1no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTakahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. ISMVL 1994: 19-26

Coauthor Index

1Kazutami Arimoto [12]
2Takahiro Hanyu [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
3Mitsuru Ibuki [5]
4Michitaka Kameyama [1] [2] [3]
5Hiromitsu Kimura [5]
6Takeshi Kitamura [9]
7Masatomo Miura [11]
8Masami Nakajima [12]
9Naoya Onizawa [6]
10Hirokatsu Shirahama [7] [9] [10] [12]
11Takashi Takeuchi [4]

Copyright © Tue Dec 22 17:48:42 2009 by Michael Ley (ley@uni-trier.de)