| 2008 |
|---|
| 38 | EE | Gerold Jäger,
Paul Molitor:
Algorithms and Experimental Study for the Traveling Salesman Problem of Second Order.
COCOA 2008: 211-224 |
| 2007 |
|---|
| 37 | EE | Dirk Richter,
Boris Goldengorin,
Gerold Jäger,
Paul Molitor:
Improving the Efficiency of Helsgaun's Lin-Kernighan Heuristic for the Symmetric TSP.
CAAN 2007: 99-111 |
| 36 | EE | Changxing Dong,
Paul Molitor:
What Graphs can be Efficiently Represented by BDDs?
ICCTA 2007: 128-134 |
| 2006 |
|---|
| 35 | EE | Boris Goldengorin,
Gerold Jäger,
Paul Molitor:
Some Basics on Tolerances.
AAIM 2006: 194-206 |
| 34 | EE | Boris Goldengorin,
Gerold Jäger,
Paul Molitor:
Tolerance Based Contract-or-Patch Heuristic for the Asymmetric TSP.
CAAN 2006: 86-97 |
| 33 | EE | Paul Molitor:
...was wird mit übrigens?
it - Information Technology 48(4): 247 (2006) |
| 2005 |
|---|
| 32 | EE | Paul Molitor:
Gutachter 2005.
it - Information Technology 47(6): 366- (2005) |
| 2004 |
|---|
| 31 | EE | Paul Molitor:
Gutachter 2004.
it - Information Technology 46(6): 360- (2004) |
| 2003 |
|---|
| 30 | | Martin Keim,
Rolf Drechsler,
Bernd Becker,
Michael Martin,
Paul Molitor:
Polynomial Formal Verification of Multipliers.
Formal Methods in System Design 22(1): 39-58 (2003) |
| 29 | EE | Heinz Zemanek,
Johannes Oldenbourg,
Paul Molitor,
Klaus Küspert,
Kurt Rothermel:
Zum neuen Jahrgang.
it - Information Technology 45(1): 3-5 (2003) |
| 2002 |
|---|
| 28 | EE | Robby Schönfeld,
Paul Molitor:
What are the samples for learning efficient routing heuristics? [MCM routing].
APCCAS (1) 2002: 267-272 |
| 27 | | Janett Mohnke,
Paul Molitor,
Sharad Malik:
Limits of Using Signatures for Permutation Independent Boolean Comparison.
Formal Methods in System Design 21(2): 167-191 (2002) |
| 2001 |
|---|
| 26 | EE | Jörg Ritter,
Paul Molitor:
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's.
FPGA 2001: 201-206 |
| 25 | EE | Janett Mohnke,
Paul Molitor,
Sharad Malik:
Application of BDDs in Boolean matching techniques for formal logic combinational verification.
STTT 3(2): 207-216 (2001) |
| 2000 |
|---|
| 24 | EE | Sandro Wefel,
Paul Molitor:
Prove that a faulty multiplier is faulty!?
ACM Great Lakes Symposium on VLSI 2000: 43-46 |
| 23 | EE | Riccardo Forth,
Paul Molitor:
An efficient heuristic for state encoding minimizing the BDD representations of the transistion relations of finite state machines.
ASP-DAC 2000: 61-66 |
| 22 | EE | Wolfgang Günther,
Robby Schönfeld,
Bernd Becker,
Paul Molitor:
k-Layer Straightline Crossing Minimization by Speeding Up Sifting.
Graph Drawing 2000: 253-258 |
| 21 | EE | Laura Heinrich-Litan,
Paul Molitor:
Least Upper Bounds for the Size of OBDDs Using Symmetry Properties.
IEEE Trans. Computers 49(4): 360-368 (2000) |
| 1999 |
|---|
| 20 | EE | Christian Matuszewski,
Robby Schönfeld,
Paul Molitor:
Using Sifting for k -Layer Straightline Crossing Minimization.
Graph Drawing 1999: 217-224 |
| 19 | EE | Christoph Scholl,
Dirk Möller,
Paul Molitor,
Rolf Drechsler:
BDD minimization using symmetries.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 81-100 (1999) |
| 18 | EE | Janett Mohnke,
Paul Molitor,
Sharad Malik:
Establishing latch correspondence for sequential circuits using distinguishing signatures.
Integration 27(1): 33-46 (1999) |
| 1998 |
|---|
| 17 | EE | Laura Heinrich-Litan,
Ursula Fissgus,
St. Sutter,
Paul Molitor,
Thomas Rauber:
Modeling the Communication Behavior of Distributed Memory Machines by Genetic Programming.
Euro-Par 1998: 273-278 |
| 1997 |
|---|
| 16 | EE | Martin Keim,
Michael Martin,
Bernd Becker,
Rolf Drechsler,
Paul Molitor:
Polynomial Formal Verification of Multipliers.
VTS 1997: 150-157 |
| 1996 |
|---|
| 15 | EE | Laura Heinrich-Litan,
Paul Molitor,
Dirk Möller:
Least Upper Bounds on the Sizes of Symmetric Variable Order based OBDDs.
Great Lakes Symposium on VLSI 1996: 126- |
| 14 | | Tolga Asveren,
Paul Molitor:
New Crossover Methods For Sequencing Problems.
PPSN 1996: 290-299 |
| 1995 |
|---|
| 13 | EE | Christoph Scholl,
Paul Molitor:
Communication based FPGA synthesis for multi-output Boolean functions.
ASP-DAC 1995 |
| 12 | EE | Janett Mohnke,
Paul Molitor,
Sharad Malik:
Limits of using signatures for permutation independent Boolean comparison.
ASP-DAC 1995 |
| 11 | EE | Ines Peters,
Paul Molitor:
Priority driven channel pin assignment.
Great Lakes Symposium on VLSI 1995: 132- |
| 10 | EE | Bernd Becker,
Rolf Drechsler,
Paul Molitor:
On the generation of area-time optimal testable adders.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1049-1066 (1995) |
| 1994 |
|---|
| 9 | | Paul Molitor,
Uwe Sparmann,
Dorothea Wagner:
Two-Layer Wiring with Pin Preassignments is Easier if the Power Supply Nets are Already Generated.
VLSI Design 1994: 149-154 |
| 1992 |
|---|
| 8 | | Michael Kaufmann,
Paul Molitor,
Wolfgang Vogelgesang:
Performance Driven k-Layer Wiring.
STACS 1992: 489-500 |
| 1991 |
|---|
| 7 | | Paul Molitor:
A Survey on Wiring.
Elektronische Informationsverarbeitung und Kybernetik 27(1): 3-19 (1991) |
| 1990 |
|---|
| 6 | EE | Paul Molitor:
Constrained via minimization for systolic arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(5): 537-542 (1990) |
| 1987 |
|---|
| 5 | EE | Bernd Becker,
Günter Hotz,
Reiner Kolla,
Paul Molitor,
Hans-Georg Osthof:
Hierarchical Design Based on a Calculus of Nets.
DAC 1987: 649-653 |
| 4 | | Paul Molitor:
On the Contact-Minimization-Problem.
STACS 1987: 420-431 |
| 1986 |
|---|
| 3 | | Günter Hotz,
Reiner Kolla,
Paul Molitor:
On Network Algebras and Recursive Equations.
Graph-Grammars and Their Application to Computer Science 1986: 250-261 |
| 2 | | Günter Hotz,
Bernd Becker,
Reiner Kolla,
Paul Molitor:
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I.
Inform., Forsch. Entwickl. 1(1): 38-47 (1986) |
| 1 | | Günter Hotz,
Bernd Becker,
Reiner Kolla,
Paul Molitor:
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II.
Inform., Forsch. Entwickl. 1(2): 72-82 (1986) |
