Simon W. Moore

	2009
31		A. Theodore Markettos, Simon W. Moore: The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators. CHES 2009: 317-331
30		Rosemary M. Francis, Simon W. Moore: FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis. FPGA 2009: 285
	2008
29		Daniel Greenfield, Simon W. Moore: Implications of Electronics Technology Trends to Algorithm Design. BCS Int. Acad. Conf. 2008: 331-342
28		Rosemary M. Francis, Simon W. Moore, Robert D. Mullins: A Network of Time-Division Multiplexed Wiring for FPGAs. NOCS 2008: 35-44
27		Simon W. Moore, Daniel Greenfield: The next resource war: computation vs. communication. SLIP 2008: 81-86
26		Daniel Greenfield, Simon W. Moore: Fractal communication in software data dependency graphs. SPAA 2008: 116-118
	2007
25		Robert D. Mullins, Simon W. Moore: Demystifying Data-Driven and Pausible Clocking Schemes. ASYNC 2007: 175-185
24		Arnab Banerjee, Robert D. Mullins, Simon W. Moore: A Power and Energy Exploration of Network-on-Chip Architectures. NOCS 2007: 163-172
23		Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon W. Moore: Implications of Rent's Rule for NoC Design and Its Fault-Tolerance. NOCS 2007: 283-294
	2006
22		Kate Taylor, Simon W. Moore: My Compiler Really Understands Me: An Adaptive Programming Language Tutor. AH 2006: 389-392
21		Robert D. Mullins, Andrew West, Simon W. Moore: The design and implementation of a low-latency on-chip network. ASP-DAC 2006: 164-169
20		Petros Oikonomakos, Jacques J. A. Fournier, Simon W. Moore: Implementing Cryptography on TFT Technology for Secure Display Applications. CARDIS 2006: 32-47
19		Petros Oikonomakos, Simon W. Moore: An Asynchronous PLA with Improved Security Characteristics. DSD 2006: 257-264
18		Jacques J. A. Fournier, Simon W. Moore: Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography. DSD 2006: 439-446
17		Simon Hollis, Simon W. Moore: RasP: An Area-efficient, On-chip Network. ICCD 2006
16		Simon Hollis, Simon W. Moore: An area-efficient, pulse-based interconnect. ISCAS 2006
15		Simon Hollis, Simon W. Moore: An Asynchronous Interconnect Architecture for Device Security Enhancement. VLSI Design 2006: 209-215
	2005
14		Scott Fairbanks, Simon W. Moore: Self-Timed Circuitry for Global Clocking. ASYNC 2005: 86-96
13		Huiyun Li, A. Theodore Markettos, Simon W. Moore: Security Evaluation Against Electromagnetic Analysis at Design Time. CHES 2005: 280-292
12		Jacques J. A. Fournier, Simon W. Moore: A Vector Approach to Cryptography Implementation. DRMTICS 2005: 277-297
	2004
11		Scott Fairbanks, Simon W. Moore: Analog Micropipeline Rings for High Precision Timing. ASYNC 2004: 41-50
10		Robert D. Mullins, Andrew West, Simon W. Moore: Low-Latency Virtual-Channel Routers for On-Chip Networks. ISCA 2004: 188-197
	2003
9		Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor: Security Evaluation of Asynchronous Circuits. CHES 2003: 137-151
8		Simon W. Moore, Ross J. Anderson, Robert D. Mullins, George S. Taylor, Jacques J. A. Fournier: Balanced self-checking asynchronous logic for smart card applications. Microprocessors and Microsystems 27(9): 421-430 (2003)
	2002
7		Simon W. Moore, Robert D. Mullins, Paul A. Cunningham, Ross J. Anderson, George S. Taylor: Improving Smart Card Security Using Self-Timed Circuits. ASYNC 2002: 211-
6		George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson: Point to Point GALS Interconnect. ASYNC 2002: 69-75
5		Panit Watcharawitch, Simon W. Moore: JMA: The Java-Multithreading Architecture for Embedded Processors. ICCD 2002: 527-
	2001
4		Simon W. Moore: Protecting Consumer Security Devices. E-smart 2001: 1
	2000
3		George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson: An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems. ASYNC 2000: 45-51
2		Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson: Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems. ICCD 2000: 73-
	1995
1		Simon W. Moore, Brian T. Graham: Tagged Up/Down Sorter - A Hardware Priority Queue. Comput. J. 38(9): 695-703 (1995)

Coauthor Index

1	Ross J. Anderson	[7] [8]
2	Arnab Banerjee	[23] [24]
3	Paul A. Cunningham	[2] [7]
4	Scott Fairbanks	[11] [14]
5	Jacques J. A. Fournier	[8] [9] [12] [18] [20]
6	Rosemary M. Francis	[28] [30]
7	Brian T. Graham	[1]
8	Daniel Greenfield	[23] [26] [27] [29]
9	Simon Hollis	[15] [16] [17]
10	Jeong-Gun Lee	[23]
11	Huiyun Li	[9] [13]
12	A. Theodore Markettos	[13] [31]
13	Robert D. Mullins	[2] [6] [7] [8] [9] [10] [21] [24] [25] [28]
14	Petros Oikonomakos	[19] [20]
15	Peter Robinson	[2] [3] [6]
16	George S. Taylor	[2] [3] [6] [7] [8] [9]
17	Kate Taylor	[22]
18	Panit Watcharawitch	[5]
19	Andrew West	[10] [21]
20	Steve Wilcox	[3]

Colors in the list of coauthors