Jaime H. Moreno

	2009
15		John P. Karidis, José E. Moreira, Jaime H. Moreno: True value: assessing and optimizing the cost of computing at the data center level. Conf. Computing Frontiers 2009: 185-192
	2006
14		Jaime H. Moreno: Chip-level integration: the new frontier for microprocessor architecture. SPAA 2006: 328
	2004
13		Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno: Design methodology for semi custom processor cores. ACM Great Lakes Symposium on VLSI 2004: 448-452
	2003
12		Jaime H. Moreno, Praveen K. Murthy, Thomas M. Conte, Paolo Faraboschi: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003 ACM 2003
11		Hillery C. Hunter, Jaime H. Moreno: A new look at exploiting data parallelism in embedded systems. CASES 2003: 159-169
10		Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno: Reducing instruction fetch energy with backwards branch control information and buffering. ISLPED 2003: 322-325
9		Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter: An innovative low-power high-performance programmable signal processor for digital communications. IBM Journal of Research and Development 47(2-3): 299-326 (2003)
	1999
8		Mayan Moudgill, P. Bose, Jaime H. Moreno: Validation of Turandot, a fast processor model for microarchitecture exploration. IPCCC 1999: 451-457
	1997
7		Jaime H. Moreno, Mayan Moudgill: Scalable Instruction-Level Parallelism Through Tree-Instructions. International Conference on Supercomputing 1997: 1-11
6		Jaime H. Moreno, Mayan Moudgill, Kemal Ebcioglu, Erik R. Altman, C. Brian Hall, Rene Miranda, Shyh-Kwei Chen, Arkady Polyak: Simulation/evaluation environment for a VLIW processor architecture. IBM Journal of Research and Development 41(3): 287-302 (1997)
	1993
5		Tomás Lang, Jaime H. Moreno: Introduction. VLSI Signal Processing 5(1): 6 (1993)
	1991
4		Jaime H. Moreno, Miguel E. Figueroa, Tomás Lang: Linear pseudosystolic array for partitioned matrix algorithms. VLSI Signal Processing 3(3): 201-214 (1991)
	1990
3		Jaime H. Moreno, Tomás Lang: Matric Computations on Systolic-Type Meshes. IEEE Computer 23(4): 32-51 (1990)
	1988
2		Jaime H. Moreno, Tomás Lang: Graph-based Partitioning of Matrix Algorithms for Systolic Arrays: Application to Transitive Closure. ICPP (1) 1988: 28-31
	1986
1		Jaime H. Moreno, Tomás Lang: Replication and Pipelining in Multiple-Instance Algorithms. ICPP 1986: 285-292

Coauthor Index

1	Erik R. Altman	[6]
2	Sameh W. Asaad	[9] [10] [13]
3	Shay Ben-David	[9]
4	Marina Biberstein	[9]
5	P. Bose	[8]
6	Shyh-Kwei Chen	[6]
7	Thomas M. Conte	[12]
8	Jeff H. Derby	[9]
9	Kemal Ebcioglu	[6]
10	Paolo Faraboschi	[12]
11	Miguel E. Figueroa	[4]
12	Thomas W. Fox	[9] [13]
13	Amir B. Geva	[9]
14	Anne-Marie Haen	[13]
15	C. Brian Hall	[6]
16	Hillery C. Hunter	[9] [11]
17	Krishnan Kailas	[9]
18	John P. Karidis	[15]
19	Tomás Lang	[1] [2] [3] [4] [5]
20	Daniel Littrell	[9] [13]
21	Rene Miranda	[6]
22	José E. Moreira	[15]
23	Mayan Moudgill	[6] [7] [8]
24	Praveen K. Murthy	[12]
25	Dorit Naishlos	[9]
26	Fredy D. Neeser	[9]
27	Arkady Polyak	[6]
28	Jude A. Rivers	[10]
29	Uzi Shvadron	[9]
30	Malcolm S. Ware	[9]
31	John-David Wellman	[10]
32	Ayal Zaks	[9]
33	Victor V. Zyuban	[9] [13]

Colors in the list of coauthors