| 2009 | ||
|---|---|---|
| 27 | Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho: Design methods for pipeline & delta-sigma A-to-D converters with convex optimization. ASP-DAC 2009: 690-695 | |
| 26 | Daisuke Atuti, Takashi Morie, Kazuyuki Aihara: A Current-Sampling-Mode CMOS Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach. IEICE Transactions 92-A(5): 1308-1315 (2009) | |
| 25 | Hideki Tanaka, Takashi Morie, Kazuyuki Aihara: A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function. IEICE Transactions 92-A(7): 1690-1698 (2009) | |
| 2008 | ||
| 24 | Daisuke Atuti, Kazuki Nakada, Takashi Morie: CMOS pulse-modulation circuit implementation of phase-locked loop neural networks. ISCAS 2008: 2174-2177 | |
| 2007 | ||
| 23 | Haichao Liang, Takashi Morie, Youhei Suzuki, Kazuki Nakada, Tsutomu Miki, Hatsuo Hayashi: An FPGA-based CollisionWarning System Using Hybrid Approach. HIS 2007: 30-35 | |
| 22 | Osamu Nomura, Takashi Morie: Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach. ICONIP (1) 2007: 1081-1090 | |
| 21 | Shiro Dosho, Naoshi Yanagisawa, Kazuaki Sogawa, Yuji Yamada, Takashi Morie: An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter. IEICE Transactions 90-C(6): 1197-1202 (2007) | |
| 2006 | ||
| 20 | Daisuke Atuti, Takashi Morie, Kazuyuki Aihara: A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Driven by Quantized Nonlinear Waveforms. APCCAS 2006: 1959-1963 | |
| 19 | Kan'ya Sasaki, Takashi Morie, Atsushi Iwata: A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory. IEICE Transactions 89-C(11): 1637-1644 (2006) | |
| 18 | Shiro Dosho, Takashi Morie, Koji Okamoto, Yuji Yamada, Kazuaki Sogawa: A -90 dBc@ 10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit. IEICE Transactions 89-C(6): 739-745 (2006) | |
| 17 | Osamu Nomura, Takashi Morie, Keisuke Korekado, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata: An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture. IEICE Transactions 89-C(6): 781-791 (2006) | |
| 2005 | ||
| 16 | Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata: A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. ICNC (3) 2005: 1006-1014 | |
| 15 | Youngjae Kim, Takashi Morie: A pixel-parallel anisotropic diffusion algorithm for subjective contour generation. ISCAS (5) 2005: 4237-4240 | |
| 2004 | ||
| 14 | Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata: A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. KES 2004: 995-1001 | |
| 13 | Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata: A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture. Journal of Intelligent and Fuzzy Systems 15(3-4): 173-179 (2004) | |
| 2003 | ||
| 12 | Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata: A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. KES 2003: 169-176 | |
| 2002 | ||
| 11 | Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata: A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. APCCAS (2) 2002: 197-200 | |
| 10 | Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata: Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. VLSI Design 2002: 71-76 | |
| 2001 | ||
| 9 | Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata: Test circuits for substrate noise evaluation in CMOS digital ICs. ASP-DAC 2001: 13-14 | |
| 8 | Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata: Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. ISQED 2001: 482-487 | |
| 7 | Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata: An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. NIPS 2001: 1115-1122 | |
| 2000 | ||
| 6 | Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata: A smart imager for the vision processing front-END. ASP-DAC 2000: 19-20 | |
| 5 | Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata: An arbitrary chaos generator core curcuit using PWM/PPM signals. ASP-DAC 2000: 23-24 | |
| 4 | Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata: Measurements and analyses of substrate noise waveform inmixed-signal IC environment. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 671-678 (2000) | |
| 1999 | ||
| 3 | Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie: A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. VLSI 1999: 77-88 | |
| 1998 | ||
| 2 | Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata: Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. ICONIP 1998: 582-585 | |
| 1 | Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata: Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. ICONIP 1998: 586-589 | |