 | 2007 |
|---|
| 4 |       | Malay K. Ganai,
Akira Mukaiyama,
Aarti Gupta,
Kazutoshi Wakabayashi:
Synthesizing "Verification Aware" Models: Why and How?
VLSI Design 2007: 50-56 |
| 2002 |
|---|
| 3 | | Aarti Gupta,
Albert E. Casavant,
Pranav Ashar,
X. G. Liu,
Akira Mukaiyama,
Kazutoshi Wakabayashi:
Property-Specific Testbench Generation for Guided Simulation.
VLSI Design 2002: 524- |
| 2001 |
|---|
| 2 | | Albert E. Casavant,
Aarti Gupta,
S. Liu,
Akira Mukaiyama,
Kazutoshi Wakabayashi,
Pranav Ashar:
Property-specific witness graph generation for guided simulation.
DATE 2001: 799 |
| 1998 |
|---|
| 1 | | Pranav Ashar,
Subhrajit Bhattacharya,
Anand Raghunathan,
Akira Mukaiyama:
Verification of RTL generated from scheduled behavior in a high-level synthesis flow.
ICCAD 1998: 517-524 |
