 | 2008 |
|---|
| 10 |       | Yuichiro Murachi,
Kusuke Mizuno,
Junichi Miyakoshi,
Masaki Hamamoto,
Takahiro Iinuma,
Tomokazu Ishihara,
Fang Yin,
Jangchung Lee,
Tetsuya Kamino,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding.
ISCAS 2008: 848-851 |
| 9 | | Hidehiro Fujiwara,
Koji Nii,
Hiroki Noguchi,
Junichi Miyakoshi,
Yuichiro Murachi,
Yasuhiro Morita,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering.
IEEE Trans. VLSI Syst. 16(6): 620-627 (2008) |
| 8 | | Yuichiro Murachi,
Yuki Fukuyama,
Ryo Yamamoto,
Junichi Miyakoshi,
Hiroshi Kawaguchi,
Hajime Ishihara,
Masayuki Miyama,
Yoshio Matsuda,
Masahiko Yoshimoto:
A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition.
IEICE Transactions 91-C(4): 457-464 (2008) |
| 7 | | Yuichiro Murachi,
Junichi Miyakoshi,
Masaki Hamamoto,
Takahiro Iinuma,
Tomokazu Ishihara,
Fang Yin,
Jangchung Lee,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer.
IEICE Transactions 91-C(4): 465-478 (2008) |
| 2006 |
|---|
| 6 | | Hidehiro Fujiwara,
Koji Nii,
Junichi Miyakoshi,
Yuichiro Murachi,
Yasuhiro Morita,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering.
ISLPED 2006: 61-66 |
| 5 | | Junichi Miyakoshi,
Yuichiro Murachi,
Masaki Hamamoto,
Takahiro Iinuma,
Tomokazu Ishihara,
Hiroshi Kawaguchi,
Masahiko Yoshimoto,
Tetsuro Matsuno:
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.
VLSI-SoC 2006: 192-197 |
| 4 | | Junichi Miyakoshi,
Yuichiro Murachi,
Tetsuro Matsuno,
Masaki Hamamoto,
Takahiro Iinuma,
Tomokazu Ishihara,
Hiroshi Kawaguchi,
Masayuki Miyama,
Masahiko Yoshimoto:
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture.
IEICE Transactions 89-A(12): 3623-3633 (2006) |
| 3 | | Junichi Miyakoshi,
Yuichiro Murachi,
Tomokazu Ishihara,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.
IEICE Transactions 89-C(11): 1629-1636 (2006) |
| 2005 |
|---|
| 2 | | Yuichiro Murachi,
Koji Hamano,
Tetsuro Matsuno,
Junichi Miyakoshi,
Masayuki Miyama,
Masahiko Yoshimoto:
A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application.
IEICE Transactions 88-A(12): 3492-3499 (2005) |
| 1 | | Junichi Miyakoshi,
Yuichiro Murachi,
Koji Hamano,
Tetsuro Matsuno,
Masayuki Miyama,
Masahiko Yoshimoto:
A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation.
IEICE Transactions 88-C(4): 559-569 (2005) |
