| 2006 | ||
|---|---|---|
| 2 | R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopal, N. Guruprasad, K. Subbarangaiah, Taher Abbasi, D. V. R. Murthy, P. Krishna Prasad, D. R. Gude: A Comprehensive SoC Design Methodology for Nanometer Design Challenges. VLSI Design 2006: 15-17 | |
| 1999 | ||
| 1 | D. V. R. Murthy, S. Ramachandran, S. Srinivasan: Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs. VLSI Design 1999: 336-339 | |