 | 2004 |
|---|
| 12 |       | Ashok K. Murugavel,
N. Ranganathan:
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization.
VLSI Design 2004: 195-200 |
| 11 | | Ashok K. Murugavel,
N. Ranganathan:
Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis.
VLSI Design 2004: 670- |
| 2003 |
|---|
| 10 | | N. Ranganathan,
Ashok K. Murugavel:
A low power scheduler using game theory.
CODES+ISSS 2003: 126-131 |
| 9 | | N. Ranganathan,
Ashok K. Murugavel:
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization.
ICCD 2003: 276-281 |
| 8 | | Ashok K. Murugavel,
N. Ranganathan:
A Game-Theoretic Approach for Binding in Behavioral Synthesis.
VLSI Design 2003: 452- |
| 7 | | Ashok K. Murugavel,
N. Ranganathan:
Petri net modeling of gate and interconnect delays for power estimation.
IEEE Trans. VLSI Syst. 11(5): 921-927 (2003) |
| 6 | | Ashok K. Murugavel,
N. Ranganathan:
A game theoretic approach for power optimization during behavioral synthesis.
IEEE Trans. VLSI Syst. 11(6): 1031-1043 (2003) |
| 2002 |
|---|
| 5 | | Ashok K. Murugavel,
N. Ranganathan:
Petri net modeling of gate and interconnect delays for power estimation.
DAC 2002: 455-460 |
| 4 | | Ashok K. Murugavel,
N. Ranganathan:
Power estimation of sequential circuits using hierarchical colored hardware petri net modeling.
ISLPED 2002: 267-270 |
| 3 | | Ashok K. Murugavel,
N. Ranganathan:
A Real Delay Switching Activity Simulator Based on Petri Net Modeling.
VLSI Design 2002: 181-186 |
| 2 | | Ashok K. Murugavel,
N. Ranganathan,
Ramamurti Chandramouli,
Srinath Chavali:
Least-square estimation of average power in digital CMOS circuits.
IEEE Trans. VLSI Syst. 10(1): 55-58 (2002) |
| 2001 |
|---|
| 1 | | Ashok K. Murugavel,
N. Ranganathan,
Ramamurti Chandramouli,
Srinath Chavali:
Average Power in Digital CMOS Circuits using Least Square Estimation.
VLSI Design 2001: 215-220 |
