Onur Mutlu

	2009
39		M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt: Accelerating critical section execution with asymmetric multi-core architectures. ASPLOS 2009: 253-264
38		Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu: Express Cube Topologies for on-Chip Interconnects. HPCA 2009: 163-174
37		Eiman Ebrahimi, Onur Mutlu, Yale N. Patt: Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. HPCA 2009: 7-17
36		Thomas Moscibroda, Onur Mutlu: A case for bufferless routing in on-chip networks. ISCA 2009: 196-207
35		Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger: Architecting phase change memory as a scalable dram alternative. ISCA 2009: 2-13
34		José A. Joao, Onur Mutlu, Yale N. Patt: Flexible reference-counting-based hardware acceleration for garbage collection. ISCA 2009: 418-428
	2008
33		David Christie, Alan Lee, Onur Mutlu, Benjamin G. Zorn: 4th International Symposium on Workload Characterization (IISWC 2008), Seattle, Washington, USA, September 14-16, 2008 IEEE 2008
32		José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, Yale N. Patt: Improving the performance of object-oriented languages with dynamic predication of indirect jumps. ASPLOS 2008: 80-90
31		Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt: Performance-aware speculation control using wrong path usefulness prediction. HPCA 2008: 39-49
30		Engin Ipek, Onur Mutlu, José F. Martínez, Rich Caruana: Self-Optimizing Memory Controllers: A Reinforcement Learning Approach. ISCA 2008: 39-50
29		Onur Mutlu, Thomas Moscibroda: Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems. ISCA 2008: 63-74
28		Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt: Prefetch-Aware DRAM Controllers. MICRO 2008: 200-209
27		Kypros Constantinides, Onur Mutlu, Todd M. Austin: Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. MICRO 2008: 282-293
26		Thomas Moscibroda, Onur Mutlu: Distributed order scheduling and its application to multi-core dram controllers. PODC 2008: 365-374
	2007
25		Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt: Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors. CGO 2007: 367-378
24		Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt: Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. HPCA 2007: 63-74
23		Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn: VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. ISCA 2007: 424-435
22		Onur Mutlu, Thomas Moscibroda: Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. MICRO 2007: 146-160
21		Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco: Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. MICRO 2007: 97-108
20		José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt: Dynamic Predication of Indirect Jumps. Computer Architecture Letters 6(2): 25-28 (2007)
19		Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt: Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication. IEEE Micro 27(1): 94-104 (2007)
	2006
18		Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt: 2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set. CGO 2006: 159-172
17		Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt: A Case for MLP-Aware Cache Replacement. ISCA 2006: 167-178
16		Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt: Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. MICRO 2006: 53-64
15		Onur Mutlu, Hyesoon Kim, Yale N. Patt: Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance. IEEE Micro 26(1): 10-20 (2006)
14		Hyesoon Kim, Onur Mutlu, Yale N. Patt, Jared Stark: Wish Branches: Enabling Adaptive and Aggressive Predicated Execution. IEEE Micro 26(1): 48-58 (2006)
13		Onur Mutlu, Hyesoon Kim, Yale N. Patt: Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses. IEEE Trans. Computers 55(12): 1491-1508 (2006)
	2005
12		Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt: Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors. DSN 2005: 434-443
11		Onur Mutlu, Hyesoon Kim, Yale N. Patt: Techniques for Efficient Processing in Runahead Execution Engines. ISCA 2005: 370-381
10		Onur Mutlu, Hyesoon Kim, Yale N. Patt: Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. MICRO 2005: 233-244
9		Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt: Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. MICRO 2005: 43-54
8		Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt: On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor. Computer Architecture Letters 4(1): 2 (2005)
7		Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt: An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors. IEEE Trans. Computers 54(12): 1556-1571 (2005)
6		Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt: Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. International Journal of Parallel Programming 33(5): 529-559 (2005)
	2004
5		David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt: Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. MICRO 2004: 119-128
4		Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt: Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance. SBAC-PAD 2004: 2-9
3		Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt: Understanding the effects of wrong-path memory references on processor performance. WMPI 2004: 56-64
	2003
2		Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt: Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. HPCA 2003: 129-140
1		Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt: Runahead Execution: An Effective Alternative to Large Instruction Windows. IEEE Micro 23(6): 20-25 (2003)

Coauthor Index

1	Rishi Agarwal	[32]
2	David N. Armstrong	[3] [4] [5] [6] [7]
3	Todd M. Austin	[21] [27]
4	Valeria Bertacco	[21]
5	Doug Burger	[35]
6	Rich Caruana	[30]
7	David Christie	[33]
8	Robert S. Cohn (Robert Cohn)	[23]
9	Kypros Constantinides	[21] [27]
10	Eiman Ebrahimi	[37]
11	Boris Grot	[38]
12	Joel Hestness	[38]
13	Engin Ipek	[30] [35]
14	José A. Joao	[16] [19] [20] [23] [25] [32] [34]
15	Stephen W. Keckler	[38]
16	Hyesoon Kim	[3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] [16] [18] [19] [20] [23] [24] [25] [31] [32]
17	Alan Lee	[33]
18	Benjamin C. Lee	[35]
19	Chang Joo Lee	[23] [28] [31]
20	Daniel N. Lynch	[17]
21	José F. Martínez	[30]
22	Thomas Moscibroda	[22] [26] [29] [36]
23	Veynu Narasiman	[28]
24	Yale N. Patt	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [23] [24] [25] [28] [31] [32] [34] [37] [39]
25	Moinuddin K. Qureshi	[12] [17] [39]
26	Santhosh Srinath	[24]
27	Jared Stark	[1] [2] [8] [9] [14]
28	M. Aater Suleman	[18] [39]
29	Chris Wilkerson	[1] [2]
30	Benjamin G. Zorn	[33]

Colors in the list of coauthors