 | 2008 |
|---|
| 14 |       | Xiaolin Chen,
Cedric Nishan Canagarajah,
Raffaele Vitulli,
José L. Núñez-Yáñez:
Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture.
ARC 2008: 332-337 |
| 13 | | Mohammad Hosseinabady,
José L. Núñez-Yáñez:
Fault-tolerant dynamically reconfigurable NoC-based SoC.
ASAP 2008: 31-36 |
| 12 | | Izhar Zaidi,
Atukem Nabina,
Cedric Nishan Canagarajah,
José L. Núñez-Yáñez:
Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration.
DSD 2008: 592-598 |
| 11 | | Izhar Zaidi,
Atukem Nabina,
Cedric Nishan Canagarajah,
José L. Núñez-Yáñez:
Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor.
FPL 2008: 547-550 |
| 10 | | Xiaofeng Wu,
Vassilios A. Chouliaras,
José L. Núñez-Yáñez,
R. M. Goodall:
A Novel Delta Sigma Control System Processor and Its VLSI Implementation.
IEEE Trans. VLSI Syst. 16(3): 217-228 (2008) |
| 9 | | Vassilios A. Chouliaras,
Vincent M. Dwyer,
Shahrukh Agha,
José L. Núñez-Yáñez,
D. Reisis,
K. Nakos,
K. Manolopoulos:
Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study.
Integration 41(1): 135-152 (2008) |
| 2007 |
|---|
| 8 | | José L. Núñez-Yáñez,
Vassilios A. Chouliaras,
Jiri Gaisler:
Dynamic Voltage Scaling in a FPGA-based System-on-Chip.
FPL 2007: 459-462 |
| 7 | | R. Stapenhurst,
K. Maharatna,
Jimson Mathew,
José L. Núñez-Yáñez,
Dhiraj K. Pradhan:
On the Hardware Reduction of z-Datapath of Vectoring CORDIC.
ISCAS 2007: 3002-3005 |
| 2006 |
|---|
| 6 | | Xiaofeng Wu,
Vassilios A. Chouliaras,
José L. Núñez-Yáñez,
Roger Goodall,
Tanya Vladimirova:
A Novel Processor Architecture for Real-Time Control.
Asia-Pacific Computer Systems Architecture Conference 2006: 270-280 |
| 2005 |
|---|
| 5 | | Tom R. Jacobs,
José L. Núñez-Yáñez:
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor.
ASAP 2005: 405-410 |
| 4 | | José L. Núñez-Yáñez,
Vassilios A. Chouliaras:
Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec.
ASAP 2005: 411-416 |
| 3 | | Vassilios A. Chouliaras,
Tom R. Jacobs,
Ashwin K. Kumaraswamy,
José L. Núñez-Yáñez:
Configurable Multiprocessors for High-Performance MPEG-4 Video Coding.
ISVLSI 2005: 272-273 |
| 2 |  | K. Koutsomyti,
S. R. Parr,
Vassilios A. Chouliaras,
José L. Núñez-Yáñez:
Applying data-parallel and scalar optimizations for the efficient implementation of the G.729A and G.723.1 speech coding standards.
SIP 2005: 39-44 |
| 1 | | José L. Núñez-Yáñez,
Vassilios A. Chouliaras:
A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding.
IEEE Trans. Computers 54(11): 1345-1359 (2005) |
