Akira Nagoya

	2007
27		Takahiro Murooka, Akira Nagoya, Toshiaki Miyazaki, Hiroyuki Ochi, Yukihiro Nakamura: Network Processor for High-Speed Network and Quick Programming. Journal of Circuits, Systems, and Computers 16(1): 65-79 (2007)
	2003
26		Kiyoshi Oguri, Yuichiro Shibata, Akira Nagoya: Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA. Asia-Pacific Computer Systems Architecture Conference 2003: 54-68
	2001
25		Ryusuke Konishi, Hideyuki Ito, Hiroshi Nakada, Akira Nagoya, Norbert Imlig, Tsunemichi Shiozawa, Minoru Inamori, Kouichi Nagami, Kiyoshi Oguri: PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI. ASYNC 2001: 54-
24		Norbert Imlig, Tsunemichi Shiozawa, Kouichi Nagami, Yoshiki Nakane, Ryusuke Konishi, Hideyuki Ito, Akira Nagoya: Scalable space/time-shared stream-processing on the run-time reconfigurable PCA architecture. IPDPS 2001: 142
23		Hiroshi Nakada, Hideyuki Ito, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri, Tsunemichi Shiozawa, Norbert Imlig: Self-reorganising systems on VLSI circuits. ISCAS (4) 2001: 310-313
22		Takayuki Suyama, Makoto Yokoo, Hiroshi Sawada, Akira Nagoya: Solving satisfiability problems using reconfigurable computing. IEEE Trans. VLSI Syst. 9(1): 109-116 (2001)
	2000
21		Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya: An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation. ASP-DAC 2000: 253-258
20		Kazuo Aoyama, Hiroshi Sawada, Akira Nagoya, Kazuo Nakajima: A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology. FPL 2000: 665-674
19		Tsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi Nakada: An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture. FPL 2000: 805-809
18		Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya: SPFD: A new method to express functional flexibility. IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 840-849 (2000)
	1999
17		Hidehisa Nagano, Takayuki Suyama, Akira Nagoya: Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach. ASP-DAC 1999: 161-164
16		Takayuki Suyama, Makoto Yokoo, Akira Nagoya: Solving Satisfiability Problems on FPGAs Using Experimental Unit Propagation. CP 1999: 434-445
15		Akihiro Matsuura, Hidehisa Nagano, Akira Nagoya: A Method for Implementing Fractal Image Compression on Reconfigurable Architecture. FPGA 1999: 251
14		Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya: An Integrated Approach for Synthesizing LUT Networks. Great Lakes Symposium on VLSI 1999: 136-139
13		Hidehisa Nagano, Akihiro Matsuura, Akira Nagoya: An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture. IPPS/SPDP Workshops 1999: 670-678
12		Takayuki Suyama, Makoto Yokoo, Akira Nagoya: Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic. IPPS/SPDP Workshops 1999: 709-711
11		Akihiro Matsuura, Akira Nagoya: Summation Algorithms on Constrained Reconfigurable Meshes. ISPAN 1999: 400-405
	1998
10		Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya: New Methods to Find Optimal Non-Disjoint Bi-Decompositions. ASP-DAC 1998: 59-68
9		Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya: Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions. DATE 1998: 755-
8		Hidehisa Nagano, Takayuki Suyama, Akira Nagoya: Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs (Abstract). FPGA 1998: 261
	1997
7		Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya: A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor. CODES 1997: 147-152
6		Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya: Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables. Great Lakes Symposium on VLSI 1997: 39-44
5		Kaihiro Matsuura, Akira Nagoya: Formulation of the Addition-Shift-Sequence Problem and Its Complexity. ISAAC 1997: 42-51
	1996
4		Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya: A new method to express functional permissibilities for LUT based FPGAs and its applications. ICCAD 1996: 254-261
3		Takayuki Suyama, Hiroshi Sawada, Akira Nagoya: LUT-based FPGA Technology Mapping using Permissible Functions. VLSI Design 1996: 215-218
	1995
2		Hiroshi Sawada, Takayuki Suyama, Akira Nagoya: Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization. ICCAD 1995: 353-358
	1990
1		Akira Nagoya, Yukihiro Nakamura, Kiyoshi Oguri, Ryo Nomura: Multi-Level Optimization for Large Scale ASICS. ICCAD 1990: 564-567

Coauthor Index

1	Kazuo Aoyama	[20]
2	Makoto Hirao	[7]
3	Norbert Imlig	[19] [23] [24] [25]
4	Minoru Inamori	[25]
5	Hideyuki Ito	[23] [24] [25]
6	Yasufumi Itou	[7]
7	Shinji Kimura	[7]
8	Ryusuke Konishi	[23] [24] [25]
9	Akihiro Matsuura	[11] [13] [15]
10	Kaihiro Matsuura	[5]
11	Toshiaki Miyazaki	[27]
12	Takahiro Murooka	[27]
13	Kouichi Nagami	[19] [24] [25]
14	Hidehisa Nagano	[8] [13] [15] [17]
15	Hiroshi Nakada	[19] [23] [25]
16	Kazuo Nakajima	[20]
17	Yukihiro Nakamura	[1] [27]
18	Yoshiki Nakane	[24]
19	Ryo Nomura	[1]
20	Hiroyuki Ochi	[27]
21	Kiyoshi Oguri	[1] [19] [23] [25] [26]
22	Hiroshi Sawada	[2] [3] [4] [6] [9] [10] [14] [18] [20] [21] [22]
23	Yuichiro Shibata	[26]
24	Tsunemichi Shiozawa	[19] [23] [24] [25]
25	Takayuki Suyama	[2] [3] [8] [12] [16] [17] [22]
26	Katsumasa Watanabe	[7]
27	Shigeru Yamashita	[4] [6] [9] [10] [14] [18] [21]
28	Makoto Yokoo	[12] [16] [22]
29	Mitsuteru Yukishita	[7]

Colors in the list of coauthors