Yousuke Nakamura

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2007

2 Yousuke Nakamura, Kei Hiraki: Heterogeneous Functional Units for High Speed Fault-Tolerant Execution Stage. PRDC 2007: 260-263

2002

1 Yousuke Nakamura, Kei Hiraki: Highly Fault-Tolerant FPGA Processor by Degrading Strategy. PRDC 2002: 75-80

	2007
2		Yousuke Nakamura, Kei Hiraki: Heterogeneous Functional Units for High Speed Fault-Tolerant Execution Stage. PRDC 2007: 260-263
	2002
1		Yousuke Nakamura, Kei Hiraki: Highly Fault-Tolerant FPGA Processor by Degrading Strategy. PRDC 2002: 75-80

Coauthor Index

1 Kei Hiraki [1] [2]