 | 2005 |
|---|
| 12 |       | Qiang Zhu,
Ryosuke Oishi,
Takashi Hasegawa,
Tsuneo Nakata:
Integrating UML into SoC Design Process.
DATE 2005: 836-837 |
| 2004 |
|---|
| 11 | | Qiang Zhu,
Ryosuke Oishi,
Takashi Hasegawa,
Tsuneo Nakata:
System-on-chip validation using UML and CWL.
CODES+ISSS 2004: 92-97 |
| 10 | | Qiang Zhu,
Tsuneo Nakata,
Masataka Mine,
Kenichiro Kuroki,
Yoichi Endo,
Takashi Hasegawa:
System-on-Chip Verification Process Using UML.
UML Satellite Activities 2004: 138-149 |
| 2003 |
|---|
| 9 | | Tsuneo Nakata:
Multi-event algorithms and protocols for fast and robust distributed mesh provisioning and restoration.
Bell Labs Technical Journal 7(3): 23-39 (2003) |
| 2002 |
|---|
| 8 | | Tsuneo Nakata,
Akio Matsuda,
Minoru Shoji,
Shinya Kuwamura,
Qiang Zhu:
An Object-Oriented Design Process for System-on-Chip Using UML.
ISSS 2002: 249-254 |
| 7 | | Subir K. Roy,
S. Ramesh,
Supratik Chakraborty,
Tsuneo Nakata,
Sreeranga P. Rajan:
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).
VLSI Design 2002: 11-13 |
| 2001 |
|---|
| 6 | | Kwame Osei Boateng,
Hideaki Konishi,
Tsuneo Nakata:
A Method of Static Compaction of Test Stimuli.
Asian Test Symposium 2001: 137-144 |
| 2000 |
|---|
| 5 | | Subir K. Roy,
Hiroaki Iwashita,
Tsuneo Nakata:
Formal verification based on assume and guarantee approach - a case study (short paper).
ASP-DAC 2000: 77-80 |
| 4 | | Subir K. Roy,
Hiroaki Iwashita,
Tsuneo Nakata:
Dataflow Analysis for Resource Contention and Register Leakage Properties.
VLSI Design 2000: 418-423 |
| 1997 |
|---|
| 3 | | Hiroaki Iwashita,
Tsuneo Nakata:
Forward model checking techniques oriented to buggy designs.
ICCAD 1997: 400-404 |
| 1996 |
|---|
| 2 | | Hiroaki Iwashita,
Tsuneo Nakata,
Fumiyasu Hirose:
CTL model checking based on forward state traversal.
ICCAD 1996: 82-87 |
| 1994 |
|---|
| 1 | | Hiroaki Iwashita,
Satoshi Kowatari,
Tsuneo Nakata,
Fumiyasu Hirose:
Automatic test program generation for pipelined processors.
ICCAD 1994: 580-583 |
