Shigetoshi Nakatake

	2009
31		Jing Li, Bo Yang, Xiaochuan Hu, Qing Dong, Shigetoshi Nakatake: STI stress aware placement optimization based on geometric programming. ACM Great Lakes Symposium on VLSI 2009: 209-214
30		Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake: Incremental buffer insertion and module resizing algorithm using geometric programming. ACM Great Lakes Symposium on VLSI 2009: 413-416
	2008
29		Qing Dong, Shigetoshi Nakatake: Constraint-free analog placement with topological symmetry structure. ASP-DAC 2008: 186-191
28		Toru Fujimura, Shigetoshi Nakatake: Transistor-level programmable MOS analog IC with body biasing. ISCAS 2008: 153-156
27		Bo Yang, Shigetoshi Nakatake, Hiroshi Murata: Fast Shape Optimization of Metallization Patterns for DMOS Based Driver. ISQED 2008: 617-620
26		Bo Yang, Hiroshi Murata, Shigetoshi Nakatake: A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion. IEICE Transactions 91-A(2): 542-549 (2008)
	2007
25		Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh: Block placement to ensure channel routability. ACM Great Lakes Symposium on VLSI 2007: 465-468
24		Shigetoshi Nakatake: Structured Placement with Topological Regularity Evaluation. ASP-DAC 2007: 215-220
	2006
23		Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani: Adaptive Porting of Analog IPs with Reusable Conservative Properties. ISVLSI 2006: 18-23
22		Ning Fu, Mitsutoshi Mineshima, Shigetoshi Nakatake: Multi-SP: A Representation with United Rectangles for Analog Placement and Routing. ISVLSI 2006: 38-43
21		Tan Yan, Shigetoshi Nakatake, Takashi Nojima: Formulating the Empirical Strategies in Module Generation of Analog MOS Layout. ISVLSI 2006: 44-49
20		Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani: The Oct-Touched Tile: A New Architecture for Shape-Based Routing. IEICE Transactions 89-A(2): 448-455 (2006)
	2005
19		Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani: The oct-touched tile: a new architecture for shape-based routing. ACM Great Lakes Symposium on VLSI 2005: 126-129
	2004
18		Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani: A device-level placement with multi-directional convex clustering. ACM Great Lakes Symposium on VLSI 2004: 196-201
17		Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani: Abstraction and optimization of consistent floorplanning with pillar block constraints. ASP-DAC 2004: 19-24
16		Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani: Multi-level placement with circuit schema based clustering in analog IC layouts. ASP-DAC 2004: 406-411
15		Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, Shigetoshi Nakatake: A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects. ISCAS (4) 2004: 489-492
	2002
14		Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita: Chip size estimation based on wiring area. APCCAS (2) 2002: 113-118
13		Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita: Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. VLSI Design 2002: 467-472
12		Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani: Consistent floorplanning with hierarchical superconstraints. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 42-49 (2002)
	2001
11		Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani: Consistent floorplanning with super hierarchical constraints. ISPD 2001: 144-149
	2000
10		Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani: Self-reforming routing for stochastic search in VLSI interconnection layout. ASP-DAC 2000: 87-92
9		Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake: Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. VLSI Design 2000: 11
	1998
8		Shigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani: Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules. ASP-DAC 1998: 571-576
7		Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani: The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. ICCAD 1998: 267-274
6		Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita: The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. ICCAD 1998: 418-425
5		Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani: Module packing based on the BSG-structure and IC layout applications. IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 519-530 (1998)
	1996
4		Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani: Module placement on BSG-structure and IC layout applications. ICCAD 1996: 484-491
3		Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani: VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1518-1524 (1996)
	1995
2		Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani: Rectangle-packing-based module placement. ICCAD 1995: 472-479
	1994
1		Shigetoshi Nakatake, Yoji Kajitani: Channel-driven global routing with consistent placement (extended abstract). ICCAD 1994: 350-355

Coauthor Index

1	Kengo R. Azegami	[9]
2	Qing Dong	[29] [30] [31]
3	Ning Fu	[17] [19] [20] [22]
4	Toru Fujimura	[23] [28]
5	Kunihiro Fujiyoshi	[2] [3] [4] [5]
6	Masahiro Furuya	[8]
7	Xiaochuan Hu	[31]
8	Yoji Kajitani	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [16] [17] [18] [19] [20] [23]
9	Zohreh Karimi	[25]
10	Masahiro Kawakita	[6] [13] [14]
11	Keiji Kida	[15]
12	Yukiko Kubo	[10] [11] [12] [13] [14]
13	Jing Li	[30] [31]
14	Mitsutoshi Mineshima	[22]
15	Hiroshi Murata	[2] [3] [4] [5] [26] [27]
16	Takashi Nojima	[16] [18] [21] [23]
17	Koji Okazaki	[23]
18	Nobuto Ono	[23]
19	Keishi Sakanushi	[6] [7]
20	Majid Sarrafzadeh	[25]
21	Taraneh Taghavi	[25]
22	Atsushi Takahashi	[9]
23	Yasuhiro Takashima	[10] [15] [16] [17] [18] [19] [20]
24	Tan Yan	[21]
25	Bo Yang	[26] [27] [30] [31]
26	Xiaoke Zhu	[15] [16]
27	Changwen Zhuang	[15]