 | 2009 |
|---|
| 10 |       | MyeongGyu Jeong,
Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature.
ACM Great Lakes Symposium on VLSI 2009: 177-180 |
| 9 | | Kunihiro Asada,
Taku Sogabe,
Toru Nakura,
Makoto Ikeda:
Measurement of power supply noise tolerance of self-timed processor.
DDECS 2009: 128-131 |
| 8 | | Sanad Bushnaq,
Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance.
DDECS 2009: 206-209 |
| 7 | | Shingo Mandai,
Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability.
IEICE Transactions 92-C(6): 798-805 (2009) |
| 2007 |
|---|
| 6 | | Taisuke Kazama,
Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
Design of Active Substrate Noise Canceller using Power Supply di/dt Detector.
ASP-DAC 2007: 100-101 |
| 2006 |
|---|
| 5 | | Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
Autonomous di/dt Control of Power Supply for Margin Aware Operation.
IEICE Transactions 89-C(11): 1689-1694 (2006) |
| 4 | | Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply.
IEICE Transactions 89-C(3): 364-369 (2006) |
| 2005 |
|---|
| 3 | | Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
Stub vs. Capacitor for Power Supply Noise Reduction.
IEICE Transactions 88-C(1): 125-132 (2005) |
| 2 | | Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
On-chip di/dt Detector Circuit.
IEICE Transactions 88-C(5): 782-787 (2005) |
| 1 | | Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs.
IEICE Transactions 88-C(8): 1734-1739 (2005) |
