| 2010 | ||
|---|---|---|
| 33 | Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo Tellez: What makes a design difficult to route. ISPD 2010: 7-12 | |
| 32 | Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu: ITOP: integrating timing optimization within placement. ISPD 2010: 83-90 | |
| 31 | Gi-Joon Nam, Prashant Saxena: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 169-170 (2010) | |
| 2009 | ||
| 30 | Gi-Joon Nam, Prashant Saxena: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009 ACM 2009 | |
| 29 | Cliff N. Sze, Phillip Restle, Gi-Joon Nam, Charles J. Alpert: Ispd2009 clock network synthesis contest. ISPD 2009: 149-150 | |
| 2008 | ||
| 28 | David Z. Pan, Gi-Joon Nam: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008 ACM 2008 | |
| 27 | Gi-Joon Nam, Cliff C. N. Sze, Mehmet Can Yildiz: The ISPD global routing benchmark suite. ISPD 2008: 156-159 | |
| 26 | David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov: RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. ISPD 2008: 2-9 | |
| 25 | David Z. Pan, Gi-Joon Nam: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2105-2106 (2008) | |
| 24 | David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov: RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2156-2168 (2008) | |
| 2007 | ||
| 23 | Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia: Hippocrates: First-Do-No-Harm Detailed Placement. ASP-DAC 2007: 141-146 | |
| 22 | Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han: Performance modeling for early analysis of multi-core systems. CODES+ISSS 2007: 209-214 | |
| 21 | Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu: RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. DAC 2007: 453-458 | |
| 20 | Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden: ISPD placement contest updates and ISPD 2007 global routing contest. ISPD 2007: 167 | |
| 19 | Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz: The nuts and bolts of physical synthesis. SLIP 2007: 89-94 | |
| 18 | Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam: Diffusion-Based Placement Migration With Application on Legalization. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2158-2172 (2007) | |
| 2006 | ||
| 17 | Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan: An accurate sparse matrix based framework for statistical static timing analysis. ICCAD 2006: 231-236 | |
| 16 | Gi-Joon Nam: ISPD 2006 Placement Contest: Benchmark Suite and Results. ISPD 2006: 167 | |
| 15 | Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng: A Fast Hierarchical Quadratic Placement Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 678-691 (2006) | |
| 2005 | ||
| 14 | Charles J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet Can Yildiz: Placement stability metrics. ASP-DAC 2005: 1144-1147 | |
| 13 | Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia: A semi-persistent clustering technique for VLSI circuit placement. ISPD 2005: 200-207 | |
| 12 | Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz: The ISPD2005 placement contest and benchmark suite. ISPD 2005: 216-220 | |
| 11 | Seungbae Lee, Gi-Joon Nam, Junseok Chae, Hanseup Kim, Alan J. Drake: Two-dimensional position detection system with MEMS accelerometers, readout circuitry, and microprocessor for padless mouse applications. IEEE Trans. VLSI Syst. 13(10): 1167-1178 (2005) | |
| 2004 | ||
| 10 | Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar: A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints. IEEE Trans. Computers 53(6): 688-696 (2004) | |
| 2003 | ||
| 9 | Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia: Effective free space management for cut-based placement via analytical constraint generation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1343-1353 (2003) | |
| 2002 | ||
| 8 | Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. FPL 2002: 360-369 | |
| 7 | Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia: Free space management for cut-based placement. ICCAD 2002: 746-751 | |
| 6 | Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: A new FPGA detailed routing approach via search-based Booleansatisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 21(6): 674-684 (2002) | |
| 2001 | ||
| 5 | Seungbae Lee, Gi-Joon Nam, Junseok Chae, Hanseup Kim, Alan J. Drake: Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE Applications. DAC 2001: 852-857 | |
| 4 | Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: A boolean satisfiability-based incremental rerouting approach with application to FPGAs. DATE 2001: 560-565 | |
| 3 | Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar: A comparative study of two Boolean formulations of FPGA detailed routing constraints. ISPD 2001: 222-227 | |
| 1999 | ||
| 2 | Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. FPGA 1999: 167-175 | |
| 1 | Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: Satisfiability-Based Detailed FPGA Routing. VLSI Design 1999: 574-577 | |