| 2007 | ||
|---|---|---|
| 31 | H. Peter Hofstee, Ashwini K. Nanda, John J. Ritsko: Preface. IBM Journal of Research and Development 51(5): 501-502 (2007) | |
| 30 | Ashwini K. Nanda, J. Randal Moulic, Robert E. Hanson, Gottfried Goldrian, Michael N. Day, Bruce D. D'Amora, Sreeni Kesavarapu: Cell/B.E. blades: Building blocks for scalable, real-time, interactive, and digital media servers. IBM Journal of Research and Development 51(5): 573-582 (2007) | |
| 29 | Yang Liu, Holger Jones, Sheila Vaidya, Michael Perrone, Borivoj Tydlitát, Ashwini K. Nanda: Speech recognition systems on the Cell Broadband Engine processor. IBM Journal of Research and Development 51(5): 583-592 (2007) | |
| 2006 | ||
| 28 | Bruce D'Amora, Ashwini K. Nanda, Karen A. Magerlein, Atman Binstock, Bernard Yee: High-performance server systems and the next generation of online games. IBM Systems Journal 45(1): 103-118 (2006) | |
| 2003 | ||
| 27 | Kimberly Keeton, Russell M. Clapp, Ashwini K. Nanda: Guest Editors' Introduction: Evaluating Servers with Commercial Workloads. IEEE Computer 36(2): 29-32 (2003) | |
| 2002 | ||
| 26 | Michel Dubois, Jaeheon Jeong, Ashwini K. Nanda: Shared cache architectures for decision support systems. Perform. Eval. 49(1/4): 283-298 (2002) | |
| 2001 | ||
| 25 | Yiming Hu, Ashwini K. Nanda, Qing Yang: Measurement, Analysis and Performance Improvement of the Apache Web Server. I. J. Comput. Appl. 8(4): (2001) | |
| 24 | Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph: High-throughout coherence control and hardware messaging in Everest. IBM Journal of Research and Development 45(2): 229-244 (2001) | |
| 2000 | ||
| 23 | Ashwini K. Nanda, Kwok-Ken Mak, Krishnan Sugavanam, Ramendra K. Sahoo, Vijayaraghavan Soundararajan, T. Basil Smith: MemorIES: A Programmable, Real-Time Hardware Emulation Tool for Multiprocessor Server Design. ASPLOS 2000: 37-48 | |
| 22 | Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph: High-Throughput Coherence Controllers. HPCA 2000: 145-155 | |
| 21 | Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda: Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors. IPDPS 2000: 721-728 | |
| 1999 | ||
| 20 | Maged M. Michael, Ashwini K. Nanda: Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors. HPCA 1999: 142-151 | |
| 19 | Russell M. Clapp, Ashwini K. Nanda, Josep Torrellas: Second Workshop on Computer Architecture Evaluation Using Commercial Workloads. HPCA 1999: 322 | |
| 18 | Yiming Hu, Ashwini K. Nanda, Qing Yang: Measurement, analysis and performance improvement of the Apache Web server. IPCCC 1999: 261-267 | |
| 17 | Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim: Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors. IEEE Trans. Computers 48(2): 245-255 (1999) | |
| 1998 | ||
| 16 | Ashwini K. Nanda, Yiming Hu, Moriyoshi Ohara, Caroline Benveniste, Mark Giampapa, Maged M. Michael: The Design of COMPASS: An Execution Driven Simulator for Commercial Applications Running on Shared Memory Multiprocessors. IPPS/SPDP 1998: 503-509 | |
| 15 | Uming Ko, Poras T. Balsara, Ashwini K. Nanda: Energy optimization of multilevel cache architectures for RISC and CISC processors. IEEE Trans. VLSI Syst. 6(2): 299-308 (1998) | |
| 14 | Ashwini K. Nanda, James O. Bondi, Simonjit Dutta: The Misprediction Recovery Cache. International Journal of Parallel Programming 26(4): 383-415 (1998) | |
| 1997 | ||
| 13 | Anthony-Trung Nguyen, Pradip Bose, Kattamuri Ekanadham, Ashwini K. Nanda, Maged M. Michael: Accuracy and Speedup of Parallel Trace-Driven Architectural Simulation. IPPS 1997: 39-44 | |
| 12 | Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim, Michael L. Scott: Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors. ISCA 1997: 219-228 | |
| 11 | Laxmi N. Bhuyan, Ravi R. Iyer, Tahsin Askar, Ashwini K. Nanda, Mohan Kumar: Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor. IEEE Trans. Parallel Distrib. Syst. 8(1): 82-95 (1997) | |
| 1996 | ||
| 10 | James O. Bondi, Ashwini K. Nanda, Simonjit Dutta: Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline. MICRO 1996: 14-23 | |
| 1995 | ||
| 9 | Uming Ko, Poras T. Balsara, Ashwini K. Nanda: Energy optimization of multi-level processor cache architectures. ISLPD 1995: 45-49 | |
| 1994 | ||
| 8 | Laxmi N. Bhuyan, Ashwini K. Nanda, Tahsin Askar: Performance and Reliability of the Multistage Bus Network. ICPP (1) 1994: 26-33 | |
| 1993 | ||
| 7 | Ashwini K. Nanda, Laxmi N. Bhuyan: Design and Analysis of Cache Coherent Multistage Interconnection Networks. IEEE Trans. Computers 42(4): 458-470 (1993) | |
| 6 | Ashwini K. Nanda, Laxmi N. Bhuyan: Efficient Mapping of Applications on Cache Based Multiprocessors. J. Parallel Distrib. Comput. 19(3): 179-191 (1993) | |
| 1992 | ||
| 5 | Ashwini K. Nanda, Hong Jiang: Analysis of Directory Based Cache Coherence Schemes with Multistage Networks. ACM Conference on Computer Science 1992: 485-492 | |
| 4 | Ashwini K. Nanda, Doug DeGroot, Daniel L. Stenger: Scheduling Directed Task Graphs on Multiprocessors Using Simulated Annealing. ICDCS 1992: 20-27 | |
| 3 | Ashwini K. Nanda, Laxmi N. Bhuyan: A Formal Specification and Verification Technique for Cache Coherence Protocols. ICPP (1) 1992: 22-26 | |
| 2 | Ashwini K. Nanda, Laxmi N. Bhuyan: Mapping Applications onto a Cache Coherent Multiprocessor. SC 1992: 368-377 | |
| 1991 | ||
| 1 | Laxmi N. Bhuyan, Ashwini K. Nanda: Multistage bus network (MBN): an interconnection network for cache coherent multiprocessors. SPDP 1991: 780-787 | |