Takashi Nanya

	2008
62		Takashi Nanya, Fumihiro Maruyama, András Pataricza, Miroslaw Malek: Service Availability, 5th International Service Availability Symposium, ISAS 2008, Tokyo, Japan, May 19-21, 2008, Proceedings Springer 2008
61		Masashi Imai, Takashi Nanya: A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries. ACSD 2008: 21-26
60		Naohiro Hamada, Yuuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). ACSD 2008: 50-55
59		Bogdan Tomoyuki Nassu, Kiyonobu Uehara, Takashi Nanya: Injecting Inconsistent Values Caused by Interaction Faults for Experimental Dependability Evaluation. EDCC 2008: 3-12
58		Bogdan Tomoyuki Nassu, Takashi Nanya, Hiroshi Nakamura: Discovering Implicit Redundancies in Network Communications for Detecting Inconsistent Values. ICDM Workshops 2008: 144-153
57		Bogdan Tomoyuki Nassu, Takashi Nanya: Interaction Faults Caused by Third-Party External Systems - A Case Study and Challenges. ISAS 2008: 59-74
56		Bogdan Tomoyuki Nassu, Takashi Nanya, Hiroshi Nakamura: Detecting Inconsistent Values Caused by Interaction Faults Using Automatically Located Implicit Redundancies. PRDC 2008: 138-145
55		Roberto Jung Drebes, Takashi Nanya: Limitations of the Linux Fault Injection Framework to Test Direct Memory Access Address Errors. PRDC 2008: 146-152
	2007
54		Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya: Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. DATE 2007: 797-802
53		Wenyu Qu, Keqiu Li, Masaru Kitsuregawa, Takashi Nanya: An Efficient Method for Improving Data Collection Precision in Lifetime-adaptive Wireless Sensor Networks. ICC 2007: 3161-3166
52		Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya: Power reduction of chip multi-processors using shared resource control cooperating with DVFS. ICCD 2007: 615-622
51		Keqiu Li, Takashi Nanya, Wenyu Qu: A Minimal Access Cost-Based Multimedia Object Replacement Algorithm. IPDPS 2007: 1-7
50		Takashi Nanya: Challenges in Dependability of Networked Systems for Information Society. NPC 2007: 542
49		Wenyu Qu, Keqiu Li, Masaru Kitsuregawa, Takashi Nanya: An optimal solution for caching multimedia objects in transcoding proxies. Computer Communications 30(8): 1802-1810 (2007)
48		Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times. IEICE Transactions 90-A(12): 2790-2799 (2007)
	2006
47		Masashi Imai, Takashi Nanya: A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. ASYNC 2006: 68-77
46		Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. CIT 2006: 172
45		Keqiu Li, Takashi Nanya, Bo Jiang, Wenyu Qu: State-of-Art Techniques for Object Caching over the Internet. IMSCCS (2) 2006: 199-206
44		Bogdan Tomoyuki Nassu, Takashi Nanya: A Scenario of Tolerating Interaction Faults Between Otherwise Correct Systems. PRDC 2006: 371-372
43		Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya: Design Method of High Performance and Low Power Functional Units Considering Delay Variations. IEICE Transactions 89-A(12): 3519-3528 (2006)
	2005
42		Wenyu Qu, Keqiu Li, Hong Shen, Yingwei Jin, Takashi Nanya: The Cache Replacement Problem for Multimedia Object Caching. SKG 2005: 26
41		Keqiu Li, Wenyu Qu, Hong Shen, Di Wu, Takashi Nanya: Two Cache Replacement Algorithms Based on Association Rules and Markov Models. SKG 2005: 28
	2004
40		Masashi Imai, Metehan Özcan, Takashi Nanya: Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. ASYNC 2004: 62-71
39		Masayuki Tsukisaka, Masashi Imai, Takashi Nanya: Asynchronous Scan-Latch controller for Low Area Overhead DFT. ICCD 2004: 66-71
38		Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya: Skewed Checkpointing for Tolerating Multi-Node Failures. SRDS 2004: 116-125
	2003
37		Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya: Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. ASYNC 2003: 184-195
36		Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya: Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units. DATE 2003: 10276-10281
35		Wen Gao, Xinyu Liu, Lei Wang, Takashi Nanya: A Reconfigurable High Availability Infrastructure in Cluster for Grid. GCC (1) 2003: 576-583
34		Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya: A zero-time-overhead asynchronous four-phase controller. ISCAS (5) 2003: 205-208
33		Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya: Control signal sharing of asynchronous circuits using datapath delay information. ISCAS (5) 2003: 617-620
	2002
32		Metehan Özcan, Masashi Imai, Takashi Nanya: Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. ASYNC 2002: 109-114
31		Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya: Logic Optimization for Asynchronous SI Controllers using Transduction Method. IWLS 2002: 245-250
30		Masayuki Tsukisaka, Masashi Imai, Takashi Nanya: High Throughput Asynchronous Domino Using Dual output Buffer. IWLS 2002: 279-282
29		Hiroshi Saito, Alex Kondratyev, Takashi Nanya: Design of Asynchronous Controllers with Delay Insensitive Interface. VLSI Design 2002: 93-98
	2001
28		Hiroto Kagotani, Takuji Okamoto, Takashi Nanya: Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs. ASP-DAC 2001: 425-430
27		Nattha Sretasereekul, Takashi Nanya: Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits. ASP-DAC 2001: 437-442
26		Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno: Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. ASYNC 2001: 162-172
	2000
25		Masayuki Tsukisaka, Takashi Nanya: A testable design for asynchronous fine-grain pipeline circuits. PRDC 2000: 148-155
	1999
24		Andreas Savva, Takashi Nanya: A Gracefully Degrading Massively Parallel System Using the BSP Model, and Its Evaluation. IEEE Trans. Computers 48(1): 38-52 (1999)
	1998
23		Mohit Sahni, Takashi Nanya: On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit Design. ASP-DAC 1998: 183-189
22		Akihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya: TITAC-2: An Asynchronous 32-bit Microprocessor. ASP-DAC 1998: 319-320
21		Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya: Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic. ASYNC 1998: 262-273
20		Elias Procópio Duarte Jr., Takashi Nanya: A Hierarachical Adaptive Distributed System-Level Diagnosis Algorithm. IEEE Trans. Computers 47(1): 34-45 (1998)
19		Elias Procópio Duarte Jr., Glenn Mansfield, Takashi Nanya, Shoichi Noguchi: Improving the dependability of network management systems. Int. Journal of Network Management 8(4): 244-253 (1998)
18		Arthit Thongtak, Takashi Nanya: Stuck-at-fault testing for quasi-delay-insensitive logic circuits. Systems and Computers in Japan 29(2): 19-27 (1998)
	1997
17		Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya: TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. ICCD 1997: 288-294
16		Elias Procópio Duarte Jr., Glenn Mansfield, Takashi Nanya, Shoichi Noguchi: Non-Broadcast Network Fault-Monitoring Based on System-Level Diagnosis. Integrated Network Management 1997: 597-609
15		Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya: Verification of asynchronous logic circuit design using process algebra. Systems and Computers in Japan 28(8-9): 33-43 (1997)
	1996
14		Elias Procópio Duarte Jr., Takashi Nanya: Hierarchical Adaptive Distributed System-Level Diagnosis Applied for SNMP-based Network Fault Management. SRDS 1996: 98-107
13		Sung-Bum Park, Takashi Nanya: Automatic Synthesis of Speed-Independent Circuits from Signal Transition Graph Specifications. VLSI Design 1996: 389-392
	1995
12		Stanislaw J. Piestrak, Takashi Nanya: Towards Totally Self-Checking Delay-Insensitive Systems. FTCS 1995: 228-237
11		Andreas Savva, Takashi Nanya: Gracefully Degrading Systems Using the Bulk-Synchronous Parallel Model with Randomised Shared Memory. FTCS 1995: 299-308
	1994
10		Takashi Nanya, Yoichiro Ueno, Hiroto Kagotani, Masashi Kuwako, Akihiro Takamura: TITAC: Design of A Quasi-Delay-Insensitive Microprocessor. IEEE Design & Test of Computers 11(2): 50-63 (1994)
	1992
9		Takashi Nanya, Shin'ichi Hatakenaka, Ryuichi Onoo: Design of Fully Exercised SFS/SCD Logic Networks. FTCS 1992: 96-103
	1989
8		Takashi Nanya, Hendrik A. Goosen: The Byzantine hardware fault model. IEEE Trans. on CAD of Integrated Circuits and Systems 8(11): 1226-1231 (1989)
	1988
7		Takashi Nanya, Toshiaki Kawamura: Error/Secure/Propagating Concept and its Application to the Design of Strongly Fault-Secure Processors. IEEE Trans. Computers 37(1): 14-24 (1988)
	1987
6		Takashi Nanya, Toshiaki Kawamura: On Error Indication for Totally Self-Checking Systems. IEEE Trans. Computers 36(11): 1389-1392 (1987)
5		Takashi Nanya, Toshiaki Kawamura: A Note on Strongly Fault-Secure Sequential Circuits. IEEE Trans. Computers 36(9): 1121-1123 (1987)
	1984
4		Teruhiko Yamada, Takashi Nanya: Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults. IEEE Trans. Computers 33(8): 758-761 (1984)
	1983
3		Teruhiko Yamada, Takashi Nanya: Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines". IEEE Trans. Computers 32(5): 511-512 (1983)
	1979
2		Takashi Nanya, Yoshihiro Tohma: Universal Multicode STT State Assignments for Asynchronous Sequential Machines. IEEE Trans. Computers 28(11): 811-818 (1979)
	1978
1		Takashi Nanya, Yoshihiro Tohma: On Universal Single Transition Time Asynchronous State Assignments. IEEE Trans. Computers 27(8): 781-782 (1978)

Coauthor Index

1	Roberto Jung Drebes	[55]
2	Elias Procópio Duarte Jr.	[14] [16] [19] [20]
3	Taro Fujii	[17] [22]
4	Masahiro Fujita	[31]
5	Izumi Fukasaku	[17] [22]
6	Wen Gao	[35]
7	Hendrik A. Goosen	[8]
8	Naohiro Hamada	[48] [60]
9	Shin'ichi Hatakenaka	[9]
10	Takuro Hayashida	[38]
11	Masashi Imai	[17] [22] [26] [30] [32] [33] [34] [37] [38] [39] [40] [43] [47] [54] [61]
12	Bo Jiang	[45]
13	Yingwei Jin	[42]
14	Nattha Jindapetch	[46] [48]
15	Hiroto Kagotani	[10] [28]
16	Yoshio Kameda	[21]
17	Toshiaki Kawamura	[5] [6] [7]
18	Glenn Mansfield Keeni (Glenn Mansfield)	[16] [19]
19	Euiseok Kim	[33] [34] [36] [37]
20	Masaru Kitsuregawa	[49] [53]
21	Masaaki Kondo	[38] [43] [52] [54]
22	Alex Kondratyev	[29]
23	Masashi Kuwako	[10] [17] [22]
24	Dong-Ik Lee	[36]
25	Jeong-Gun Lee	[36]
26	Keqiu Li	[41] [42] [45] [49] [51] [53]
27	Xinyu Liu	[35]
28	Masaaki Maezawa	[21]
29	Miroslaw Malek	[62]
30	Fumihiro Maruyama	[62]
31	Chris J. Myers	[46] [48] [60]
32	Hiroshi Nakamura	[26] [31] [33] [34] [36] [37] [38] [43] [52] [54] [56] [58]
33	Bogdan Tomoyuki Nassu	[44] [56] [57] [58] [59]
34	Shoichi Noguchi	[16] [19]
35	Takuji Okamoto	[28]
36	Ryuichi Onoo	[9]
37	Motokazu Ozawa	[17] [22] [26]
38	Metehan Özcan	[32] [34] [40]
39	Sung-Bum Park	[13]
40	András Pataricza	[62]
41	Stanislaw J. Piestrak	[12]
42	Stanislav Polonsky	[21]
43	Wenyu Qu	[41] [42] [45] [49] [51] [53]
44	Mohit Sahni	[23]
45	Hiroshi Saito	[29] [31] [33] [34] [36] [37] [46] [48] [60]
46	Andreas Savva	[11] [24]
47	Hong Shen	[41] [42]
48	Atsufumi Shibayama	[15]
49	Yuuki Shiga	[60]
50	Nattha Sretasereekul	[27] [33] [34] [37]
51	Yuya Tajima	[38]
52	Akihiro Takamura	[10] [17] [22]
53	K. Thongnoo	[34]
54	Arthit Thongtak	[18]
55	Yoshihiro Tohma	[1] [2]
56	Masayuki Tsukisaka	[25] [30] [39]
57	Kiyonobu Uehara	[59]
58	Yoichiro Ueno	[10] [17] [22] [26]
59	Lei Wang	[35]
60	Kouichi Watanabe	[43]
61	Ryo Watanabe	[52] [54]
62	Di Wu	[41]
63	Teruhiko Yamada	[3] [4]
64	Tomohiro Yoneda	[15] [46] [48] [60]

Colors in the list of coauthors