 | 2009 |
|---|
| 13 |       | Magnus Jahre,
Lasse Natvig:
A light-weight fairness mechanism for chip multiprocessor memory systems.
Conf. Computing Frontiers 2009: 1-10 |
| 12 | | Magnus Jahre,
Marius Grannæs,
Lasse Natvig:
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures.
HPCC 2009: 622-629 |
| 2008 |
|---|
| 11 | | Sabri Pllana,
Siegfried Benkner,
Eduard Mehofer,
Lasse Natvig,
Fatos Xhafa:
Towards an Intelligent Environment for Programming Multi-core Computing Systems.
Euro-Par Workshops 2008: 141-151 |
| 10 | | Marius Grannæs,
Magnus Jahre,
Lasse Natvig:
Low-cost open-page prefetch scheduling in chip multiprocessors.
ICCD 2008: 390-396 |
| 2006 |
|---|
| 9 | | Haakon Dybdahl,
Marius Grannæs,
Lasse Natvig:
Cache Write-Back Schemes for Embedded Destructive-Read DRAM.
ARCS 2006: 145-159 |
| 8 | | Cyril Banino-Rokkones,
Olivier Beaumont,
Lasse Natvig:
Master-Slave Tasking on Asymmetric Networks.
Euro-Par 2006: 167-176 |
| 7 | | Haakon Dybdahl,
Per Stenström,
Lasse Natvig:
A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors.
HiPC 2006: 22-34 |
| 6 | | Haakon Dybdahl,
Per Gunnar Kjeldsberg,
Marius Grannæs,
Lasse Natvig:
Destructive-read in embedded DRAM, impact on power consumption.
J. Embedded Computing 2(2): 249-260 (2006) |
| 2004 |
|---|
| 5 | | Lasse Natvig,
Steinar Line:
Age of computers: game-based teaching of computer fundamentals.
ITiCSE 2004: 107-111 |
| 2001 |
|---|
| 4 | | Lasse Natvig:
Simulating Parallel Architectures with BSPlab.
HPCN Europe 2001: 547-550 |
| 3 | | Tormod Njølstad,
Lasse Natvig:
Experience from a 450 Students/Year Course on Digital Logic and Computer Fundamentals using FPGAs and mu-Controllers.
MSE 2001: 18-19 |
| 1994 |
|---|
| 2 |  | Lasse Natvig:
Compile and Runtime Padding: An Approach to Realising Synchronous MIMD Execution.
IFIP Congress (1) 1994: 553-558 |
| 1990 |
|---|
| 1 | | Lasse Natvig:
Logarithmic time cost optimal parallel sorting is not yet fast in practice!.
SC 1990: 486-494 |
