Zainalabedin Navabi

	2009
65		M. R. Jamali, Arash Arami, M. Dehyadegari, Caro Lucas, Zainalabedin Navabi: Emotion on FPGA: Model driven approach. Expert Syst. Appl. 36(4): 7369-7378 (2009)
	2008
64		Pejman Lotfi-Kamran, Masoud Daneshtalab, Caro Lucas, Zainalabedin Navabi: BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs. DATE 2008: 1408-1413
63		Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi: An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations. VLSI Design 2008: 409-414
62		Pejman Lotfi-Kamran, Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi: Enhanced TED: A New Data Structure for RTL Verification. VLSI Design 2008: 481-486
61		Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, Zainalabedin Navabi: Stall Power Reduction in Pipelined Architecture Processors. VLSI Design 2008: 541-546
60		Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi: A Selective Trigger Scan Architecture for VLSI Testing. IEEE Trans. Computers 57(3): 316-328 (2008)
	2007
59		Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi: RT level reliability enhancement by constructing dynamic TMRS. ACM Great Lakes Symposium on VLSI 2007: 172-175
58		Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi: Using the inter- and intra-switch regularity in NoC switch testing. DATE 2007: 361-366
57		Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi: A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. DDECS 2007: 247-250
56		Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi: Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode. DFT 2007: 21-30
55		Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi: On-Chip Verification of NoCs Using Assertion Processors. DSD 2007: 535-538
54		Parisa Razaghi, Shahrzad Mirkhani, Zainalabedin Navabi: A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library. FDL 2007: 171-176
53		Nima Honarmand, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi: APDL: A Processor Description Language For Design Space Exploration of Embedded Processors. FDL 2007: 50-55
52		Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale: Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. IOLTS 2007: 205-206
51		Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi: An Analytical Model for Reliability Evaluation of NoC Architectures. IOLTS 2007: 49-56
50		A. Shahabi, Nima Honarmand, Zainalabedin Navabi: Programmable Routing Tables for Degradable Torus-Based Networks on Chips. ISCAS 2007: 1065-1068
49		Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi: A New Approach for Design and Verification of Transaction Level Models. ISCAS 2007: 3760-3763
48		Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi: A UML Based System Level Failure Rate Assessment Technique for SoC Designs. VTS 2007: 243-248
47		Nima Honarmand, A. Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi: High Level Synthesis of Degradable ASICs Using Virtual Binding. VTS 2007: 311-317
46		Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi: Low test application time resource binding for behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. 12(2): (2007)
45		Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi: Simultaneous Reduction of Dynamic and Static Power in Scan Structures CoRR abs/0710.4653: (2007)
	2006
44		Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi: NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm. ASAP 2006: 33-38
43		Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi: A concurrent testing method for NoC switches. DATE 2006: 1171-1176
42		Hadi Esmaeilzadeh, A. Moghimi, E. Ebrahimi, Caro Lucas, Zainalabedin Navabi, A. M. Fakhraie: DCim++: a C++ library for object oriented hardware design and distributed simulation. ISCAS 2006
41		M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi: Low-power and low-latency cluster topology for local traffic NoCs. ISCAS 2006
40		Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi: An Optimized BIST Architecture for FPGA Look-Up Table Testing. ISVLSI 2006: 420-421
39		Masood Dehyadgari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi: A New Protocol Stack Model for Network on Chip. ISVLSI 2006: 440-441
38		Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi: ByZFAD: a low switching activity architecture for shift-and-add multipliers. SBCCI 2006: 179-183
37		Masoud Daneshtalab, Ali Afzali-Kusha, Ashkan Sobhani, Zainalabedin Navabi, Mohammad D. Mottaghi, Omid Fatemi: Ant colony based routing architecture for minimizing hot spots in NOCs. SBCCI 2006: 56-61
36		Ehsan Atoofian, Zainalabedin Navabi: A Test Approach for Look-Up Table Based FPGAs. J. Comput. Sci. Technol. 21(1): 141-146 (2006)
35		Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi: Scan-Based Structure with Reduced Static and Dynamic Power Consumption. J. Low Power Electronics 2(3): 477-487 (2006)
	2005
34		Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi: TED+: a data structure for microprocessor verification. ASP-DAC 2005: 567-572
33		Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi: ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. Asian Test Symposium 2005: 236-241
32		Shahrzad Mirkhani, Zainalabedin Navabi: Enhancing Fault Simulation Performance by Dynamic Fault Clustering. Asian Test Symposium 2005: 278-283
31		M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi: Sign bit reduction encoding for low power applications. DAC 2005: 214-217
30		Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi: Simultaneous Reduction of Dynamic and Static Power in Scan Structures. DATE 2005: 846-851
29		Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi: Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. DFT 2005: 389-397
28		Mostafa Naderi, Zainalabedin Navabi: Combination of Assertion and HSAT Methods For Automated Test Vectors Generation. FDL 2005: 479-485
27		Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi: Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. ISCAS (1) 2005: 424-427
26		Mohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha: A low-power scan-path architecture. ISCAS (5) 2005: 5278-5281
25		Hamid Reza Ghasemi, Zainalabedin Navabi: An Effective VHDL-AMS Simulation Algorithm with Event Partitioning. VLSI Design 2005: 762-767
24		Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi: Instruction-level test methodology for CPU core self-testing. ACM Trans. Design Autom. Electr. Syst. 10(4): 673-689 (2005)
	2004
23		Bijan Alizadeh, Zainalabedin Navabi: Property Checking based on Hierarchical Integer Equations. ACSD 2004: 26-35
22		Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi: Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores. Asian Test Symposium 2004: 158-163
21		Bijan Alizadeh, Zainalabedin Navabi: Using Integer Equations to Check PSL Properties in RT Level Design. IWSOC 2004: 83-86
20		Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin: A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores. J. Electronic Testing 20(2): 155-168 (2004)
19		Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi: Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation. J. Electronic Testing 20(6): 575-589 (2004)
	2003
18		Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi: The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. Asian Test Symposium 2003: 274-277
17		Ehsan Atoofian, Zainalabedin Navabi: A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. Asian Test Symposium 2003: 84-89
16		Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi: Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. DFT 2003: 352-360
15		Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi: Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment. Embedded Systems and Applications 2003: 139-143
14		Elham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi: Utilizing Various ADL Facets for Instruction Level CPU Test. MTV 2003: 38-
13		Morteza Fayyazi, David R. Kaeli, Zainalabedin Navabi: Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching. PDPTA 2003: 819-823
12		Elham Safi, Reihaneh Saberi, Zohreh Karimi, Zainalabedin Navabi: Processor Testing Using an ADL Description and Genetic Algorithms. VLSI-SOC 2003: 186-
11		Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi: Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. VLSI-SOC 2003: 215-220
10		Ehsan Atoofian, Zainalabedin Navabi: A Low Power BIST Architecture for FPGA Look-Up Table Testing. VLSI-SOC 2003: 394-397
	2002
9		Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi: Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. Asian Test Symposium 2002: 374-
8		Farzin Karimi, Waleed Meleis, Zainalabedin Navabi, Fabrizio Lombardi: Data Compression for System-on-Chip Testing Using ATE. DFT 2002: 166-176
	2001
7		Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi: Fault Simulation for VHDL Based Test Bench and BIST Evaluation. Asian Test Symposium 2001: 396-
6		Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi: Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation. DATE 2001: 823
5		Mohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie: An efficient BIST method for testing of embedded SRAMs. ISCAS (5) 2001: 73-76
	1993
4		Zainalabedin Navabi, Amirhooshang Hashemi, Massoud Eghtesad, Mankuan Michael Vai: Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models. CHDL 1993: 569-586
	1992
3		Zainalabedin Navabi: A high-level language for design and modeling of hardware. Journal of Systems and Software 18(1): 5-18 (1992)
	1984
2		F. J. Hill, Zainalabedin Navabi, C. H. Chiang, Duan-Ping Chen, M. Masud: Hardware Compilation from an RTL to a Storage Logic Array Target. IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 208-217 (1984)
	1981
1		F. J. Hill, R. E. Swanson, M. Masud, Zainalabedin Navabi: Structure Specification with a Procedural Hardware Description Language. IEEE Trans. Computers 30(2): 157-161 (1981)

Coauthor Index

1	Maghsoud Abbaspour	[14] [47] [53]
2	Ali Afzali-Kusha	[26] [30] [31] [35] [37] [38] [39] [41] [44] [45] [61]
3	Armin Alaghi	[40] [56] [63]
4	Mohammad Alisafaee	[26] [27]
5	Bijan Alizadeh	[21] [23] [27]
6	Arash Arami	[65]
7	Ehsan Atoofian	[10] [17] [26] [36]
8	Abbas Banaiyan	[43]
9	Alfredo Benso	[52]
10	Mahdi Nazm Bojnordi	[43]
11	Stefano Di Carlo	[52]
12	Duan-Ping Chen	[2]
13	C. H. Chiang	[2]
14	Atefe Dalirsani	[51] [58]
15	Masoud Daneshtalab	[37] [44] [55] [57] [64]
16	M. Dehyadegari	[65]
17	Masood Dehyadgari	[39]
18	E. Ebrahimi	[42]
19	Massoud Eghtesad	[4]
20	Hadi Esmaeilzadeh	[22] [24] [33] [42]
21	A. M. Fakhraie	[42]
22	Sied Mehdi Fakhraie (Seid Mehdi Fakhraie)	[5] [20]
23	Hamed Farshbaf	[7]
24	Omid Fatemi	[37] [44]
25	Mahmood Fathy	[63]
26	Morteza Fayyazi	[13]
27	Hamid Reza Ghasemi	[25]
28	Hassan Ghasemzadeh	[49]
29	Amirhooshang Hashemi	[4]
30	Safar Hatami	[26]
31	F. J. Hill	[1] [2]
32	Nima Honarmand	[47] [50] [53]
33	Arash Hooshmand	[27]
34	Mohammad Hosseinabady	[11] [16] [30] [34] [35] [43] [45] [46] [48] [51] [52] [58] [60]
35	Javid Jaffari	[30] [35] [45]
36	M. R. Jamali	[65]
37	David R. Kaeli	[13]
38	Mohammad Reza Kakoee	[49] [55] [57]
39	Farzin Karimi	[8]
40	Naghmeh Karimi	[56] [59]
41	Zohreh Karimi	[12] [14]
42	Elnaz Koopahi	[63]
43	Meisam Lavasani	[9] [19]
44	Fabrizio Lombardi	[8] [15] [18] [19] [29] [59] [60]
45	Pejman Lotfi-Kamran	[27] [34] [46] [48] [61] [62] [64]
46	Caro Lucas	[42] [64] [65]
47	Mehran Massoumi	[34] [62]
48	M. Masud	[1] [2]
49	Waleed Meleis	[8]
50	Shahrzad Mirkhani	[6] [7] [9] [19] [32] [54] [59]
51	Mohammad Mirzaei	[62]
52	A. Moghimi	[42]
53	Mohammad D. Mottaghi	[37] [38]
54	M. R. Movahedin	[20]
55	Mostafa Naderi	[27] [28]
56	Giorgio Di Natale	[52]
57	Mohammad Hossein Neishaburi	[48] [52] [55] [57]
58	Mohsen Nickray	[39]
59	Paolo Prinetto	[52]
60	Amir-Mohammad Rahmani	[61]
61	Parisa Razaghi	[54]
62	Pedram A. Riahi	[15] [16] [18] [29]
63	Reihaneh Saberi	[12]
64	Pooya Saeedi	[33]
65	Saeed Safari	[55] [57]
66	Elham Safi	[12] [14]
67	Ali-Asghar Salehpour	[61]
68	M. Saneei	[31] [41]
69	Mahshid Sedghi	[56] [63]
70	A. Shahabi	[47] [50]
71	Saeed Shamshiri	[22] [24] [27] [33]
72	Shervin Sharifi	[11] [16] [30] [35] [45] [60]
73	Hamid Shojaei	[34] [49]
74	Marjan Sirjani	[49]
75	Ashkan Sobhani	[37] [44]
76	Hasan Sohofi	[47] [53]
77	R. E. Swanson	[1]
78	Mohammad H. Tehranipour	[5] [20]
79	Mankuan Michael Vai	[4]
80	Mahnaz Sadoughi Yarandi	[40]
81	Mina Zolfy	[6] [7]

Colors in the list of coauthors