 | 2007 |
|---|
| 15 |       | John A. Nestor,
Jeremy Lavine:
L4: An FPGA-Based Accelerator for Detailed Maze Routing.
FPL 2007: 357-362 |
| 2005 |
|---|
| 14 | | John A. Nestor:
Teaching Computer Organization with HDLs: An Incremental Approach.
MSE 2005: 77-78 |
| 13 | | John A. Nestor:
L3: An FPGA-based multilayer maze routing accelerator.
Microprocessors and Microsystems 29(2-3): 87-97 (2005) |
| 2003 |
|---|
| 12 | | John A. Nestor:
FPGA Implementation of a Maze Routing Accelerator.
FPL 2003: 992-995 |
| 11 | | John A. Nestor,
David A. Rich:
Integrating Digital, Analog, and Mixed-Signal Design in an Undergraduate ECE Curriculum.
MSE 2003: 89-90 |
| 2002 |
|---|
| 10 | | John A. Nestor:
A new look at hardware maze routing.
ACM Great Lakes Symposium on VLSI 2002: 142-147 |
| 2001 |
|---|
| 9 | | John A. Nestor:
Web-Based Visualization Tools for Teaching VLSI CAD Algorithms.
MSE 2001: 100-101 |
| 1993 |
|---|
| 8 |  | Michael R. Rhinehart,
John A. Nestor:
SALSE II: A Fast Transformational Scheduler for High-level Synthesis.
ISCAS 1993: 1678-1681 |
| 7 | | John A. Nestor:
Visual register-transfer description of VLSI microarchitectures.
IEEE Trans. VLSI Syst. 1(1): 72-76 (1993) |
| 6 | | John A. Nestor,
Ganesh Krishnamoorthy:
SALSA: a new approach to scheduling with timing constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1107-1122 (1993) |
| 1992 |
|---|
| 5 | | Ganesh Krishnamoorthy,
John A. Nestor:
Data Path Allocation using an Extended Binding Model.
DAC 1992: 279-284 |
| 1990 |
|---|
| 4 | | John A. Nestor,
Ganesh Krishnamoorthy:
SALSA: A New Approach to Scheduling with Timing Constraints.
ICCAD 1990: 262-265 |
| 1989 |
|---|
| 3 | | John A. Nestor,
Bassel Soudan,
Zubair Mayet:
MIES: a microarchitecture design tool.
MICRO 1989: 217-222 |
| 1988 |
|---|
| 2 | | Donald E. Thomas,
Elizabeth M. Dirkes,
Robert A. Walker,
Jayanth V. Rajan,
John A. Nestor,
Robert L. Blackburn:
The System Architect's Workbench.
DAC 1988: 337-343 |
| 1983 |
|---|
| 1 | | Donald E. Thomas,
John A. Nestor:
Defining and Implementing a Multilevel Design Representation with Simulation Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 2(3): 135-145 (1983) |
