Nicola Nicolici

	2009
58		Adam B. Kinsman, Nicola Nicolici: Finite Precision bit-width allocation using SAT-Modulo Theory. DATE 2009: 1106-1111
57		Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris: Automated data analysis solutions to silicon debug. DATE 2009: 982-987
56		Ho Fai Ko, Nicola Nicolici: Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 285-297 (2009)
	2008
55		Ho Fai Ko, Nicola Nicolici: Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. DATE 2008: 1298-1303
54		Ho Fai Ko, Nicola Nicolici: On Automated Trigger Event Generation in Post-Silicon Validation. DATE 2008: 256-259
53		Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen: Power-Aware Testing and Test Strategies for Low Power Devices. DATE 2008
52		R. Mafi, Shahin Sirouspour, B. Moody, B. Mahdavikhah, K. Elizeh, Adam B. Kinsman, Nicola Nicolici, Mahyar Fotoohi, D. Madill: Hardware-based parallel computing for real-time haptic rendering of deformable objects. IROS 2008: 4187
51		Ho Fai Ko, Nicola Nicolici: A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test. ISQED 2008: 649-654
50		Adam B. Kinsman, Nicola Nicolici: Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing. ISQED 2008: 832-837
49		Ho Fai Ko, Nicola Nicolici: Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2092-2097 (2008)
48		Nicola Nicolici, Patrick Girard: Guest Editorial. J. Electronic Testing 24(4): 325-326 (2008)
47		Ho Fai Ko, Nicola Nicolici: Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy. J. Electronic Testing 24(4): 393-403 (2008)
	2007
46		Ehab Anis, Nicola Nicolici: Interactive presentation: Low cost debug architecture using lossy compression for silicon debug. DATE 2007: 225-230
45		Nicola Nicolici, Xiaoqing Wen: Embedded Tutorial on Low Power Test. European Test Symposium 2007: 202-210
44		Erik Jan Marinissen, Axel Jantsch, Nicola Nicolici: DATE 07 workshop on diagnostic services in NoCs. IEEE Design & Test of Computers 24(5): 510 (2007)
43		Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty: Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1539-1547 (2007)
	2006
42		Ho Fai Ko, Nicola Nicolici: RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. ICCD 2006
41		Qiang Xu, Nicola Nicolici: DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs. IEEE Trans. Computers 55(4): 470-485 (2006)
40		Adam B. Kinsman, Scott Ollivierre, Nicola Nicolici: Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison. IEEE Trans. VLSI Syst. 14(5): 537-548 (2006)
39		Qiang Xu, Nicola Nicolici: Multifrequency TAM design for hierarchical SOCs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 181-196 (2006)
	2005
38		Ho Fai Ko, Qiang Xu, Nicola Nicolici: Register-transfer level functional scan for hierarchical designs. ASP-DAC 2005: 1172-1175
37		Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty: Multi-frequency wrapper design and optimization for embedded cores under average power constraints. DAC 2005: 123-128
36		Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Synchronization overhead in SOC compressed test. IEEE Trans. VLSI Syst. 13(1): 140-152 (2005)
35		Qiang Xu, Nicola Nicolici: Modular and rapid testing of SOCs with unwrapped logic blocks. IEEE Trans. VLSI Syst. 13(11): 1275-1285 (2005)
34		Qiang Xu, Nicola Nicolici: Wrapper design for multifrequency IP cores. IEEE Trans. VLSI Syst. 13(6): 678-685 (2005)
33		Qiang Xu, Nicola Nicolici: Modular SOC testing with reduced wrapper count. IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1894-1908 (2005)
	2004
32		Qiang Xu, Nicola Nicolici: Multi-Frequency Test Access Mechanism Design for Modular SOC Testing. Asian Test Symposium 2004: 2-7
31		Ho Fai Ko, Nicola Nicolici: Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. Asian Test Symposium 2004: 454-459
30		Qiang Xu, Nicola Nicolici: Wrapper Design for Testing IP Cores with Multiple Clock Domains. DATE 2004: 416-421
29		Scott Ollivierre, Adam B. Kinsman, Nicola Nicolici: Compressed Embedded Diagnosis of Logic Cores. ICCD 2004: 534-539
28		Ho Fai Ko, Nicola Nicolici: Functional Illinois Scan Design at RTL. ICCD 2004: 78-81
27		Qiang Xu, Nicola Nicolici: Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores. ITC 2004: 1196-1202
26		Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici: Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1142-1153 (2004)
25		Nicola Nicolici, Bashir M. Al-Hashimi: Testability Trade-Offs for BIST Data Paths. J. Electronic Testing 20(2): 169-179 (2004)
	2003
24		Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Test Data Compression: The System Integrator's Perspective. DATE 2003: 10726-10731
23		Qiang Xu, Nicola Nicolici: Delay Fault Testing of Core-Based Systems-on-a-Chi. DATE 2003: 10744-10752
22		Bai Hong Fang, Nicola Nicolici: Power-Constrained Embedded Memory BIST Architecture. DFT 2003: 451-458
21		Adam B. Kinsman, Jonathan I. Hewitt, Nicola Nicolici: Embedded Compact Deterministic Test for IP-Protected Cores. DFT 2003: 519-
20		Bai Hong Fang, Qiang Xu, Nicola Nicolici: Hardware/Software Co-testing of Embedded Memories in Complex SOCs. ICCAD 2003: 599-606
19		Qiang Xu, Nicola Nicolici: On Reducing Wrapper Boundary Register Cells in Modular SOC Testing. ITC 2003: 622-631
18		Nicola Nicolici, Bashir M. Al-Hashimi: Power-Conscious Test Synthesis and Scheduling. IEEE Design & Test of Computers 20(4): 48-55 (2003)
17		Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Addressing useless test data in core-based system-on-a-chip test. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1568-1580 (2003)
16		Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Variable-length input Huffman coding for system-on-a-chip test. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 783-796 (2003)
	2002
15		Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression. DATE 2002: 604-611
14		Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici: Scan Architecture for Shift and Capture Cycle Power Reduction. DFT 2002: 129-137
13		Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici: Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding. ICCD 2002: 474-479
12		Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing. ITC 2002: 64-73
11		Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions. VTS 2002: 423-432
10		Nicola Nicolici, Bashir M. Al-Hashimi: Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits. IEEE Trans. Computers 51(6): 721-734 (2002)
9		Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici: Power profile manipulation: a new approach for reducing test application time under power constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1217-1225 (2002)
	2001
8		Nicola Nicolici, Bashir M. Al-Hashimi: Testability trade-offs for BIST RTL data paths: the case for three dimensional design space. DATE 2001: 802
7		Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici: Power constrained test scheduling using power profile manipulation. ISCAS (5) 2001: 251-254
6		Nicola Nicolici, Bashir M. Al-Hashimi: Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation. ITC 2001: 72-81
	2000
5		Nicola Nicolici, Bashir M. Al-Hashimi: Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. DATE 2000: 715-722
4		Nicola Nicolici, Bashir M. Al-Hashimi: Power conscious test synthesis and scheduling for BIST RTL data paths. ITC 2000: 662-671
3		Nicola Nicolici, Bashir M. Al-Hashimi, Andrew D. Brown, Alan Christopher Williams: BIST hardware synthesis for RTL data paths based on testcompatibility classes. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1375-1385 (2000)
	1999
2		Nicola Nicolici, Bashir M. Al-Hashimi: Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths. DATE 1999: 289-
	1998
1		Nicola Nicolici, Bashir M. Al-Hashimi: Correction to the Proof of Theorem 2 in ``Parallel Signature Analysis Design with Bounds on Aliasing. IEEE Trans. Computers 47(12): 1426 (1998)

Coauthor Index

1	Bashir M. Al-Hashimi	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [24] [25] [26] [36]
2	Ehab Anis	[46]
3	Andrew D. Brown	[3]
4	Krishnendu Chakrabarty	[37] [43]
5	K. Elizeh	[52]
6	Bai Hong Fang	[20] [22]
7	Mahyar Fotoohi	[52]
8	Patrick Girard	[48] [53]
9	Dimitris Gizopoulos	[53]
10	Paul Theo Gonciari	[11] [12] [15] [16] [17] [24] [36]
11	Jonathan I. Hewitt	[21]
12	Axel Jantsch	[44]
13	Adam B. Kinsman	[21] [29] [40] [50] [52] [58]
14	Ho Fai Ko	[28] [31] [38] [42] [47] [49] [51] [54] [55] [56]
15	D. Madill	[52]
16	R. Mafi	[52]
17	B. Mahdavikhah	[52]
18	Erik Jan Marinissen	[44]
19	B. Moody	[52]
20	Scott Ollivierre	[29] [40]
21	Paul M. Rosinger	[7] [9] [13] [14] [26]
22	Kaushik Roy	[53]
23	Shahin Sirouspour	[52]
24	Andreas G. Veneris	[57]
25	Xiaoqing Wen	[45] [53]
26	Alan Christopher Williams	[3]
27	Qiang Xu	[19] [20] [23] [27] [30] [32] [33] [34] [35] [37] [38] [39] [41] [43]
28	Yu-Shen Yang	[57]

Colors in the list of coauthors