Hideyuki Noda

	2008
11		Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Transactions 91-C(9): 1409-1418 (2008)
	2007
10		Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS 2007: 525-528
9		Fukashi Morishita, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto: A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. IEICE Transactions 90-C(4): 765-771 (2007)
8		Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Transactions 90-D(1): 334-345 (2007)
7		Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Transactions 90-D(8): 1312-1315 (2007)
	2006
6		Takayuki Gyohten, Fukashi Morishita, Isamu Hayashi, Mako Okamoto, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Yasutaka Horiba: An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. IEICE Transactions 89-C(11): 1519-1525 (2006)
5		Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto: A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Transactions 89-C(11): 1612-1619 (2006)
	2005
4		Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) 2005: 5202-5205
3		Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara: A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Transactions 88-C(10): 2020-2027 (2005)
2		Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara: Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Transactions 88-C(4): 622-629 (2005)
1		Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide: A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Transactions 88-C(6): 1332-1342 (2005)

Coauthor Index

1	Teruhiko Amano	[3]
2	Kenji Anami	[2]
3	Kazutami Arimoto	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
4	Katsumi Dosaka	[2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
5	Kazuyasu Fujishima	[2]
6	Takayuki Gyohten	[6] [9] [11]
7	Atsushi Hachisuka	[3]
8	Masaru Haraguchi	[3]
9	Isamu Hayashi	[6] [9]
10	Yasutaka Horiba	[6]
11	Kazunari Inoue	[1] [2]
12	Takashi Ipposhi	[9]
13	Masakatsu Ishizaki	[7] [8] [11]
14	Tetsushi Koide	[1] [2] [4] [5] [7] [8] [10] [11]
15	Takeshi Kumaki	[4] [7] [8] [10] [11]
16	Yasuto Kuroda	[4] [7] [8] [10] [11]
17	Shigeto Maegawa	[9]
18	Hans Jürgen Mattausch	[1] [2] [4] [5] [7] [8] [10] [11]
19	Fukashi Morishita	[3] [5] [6] [9]
20	Mako Okamoto	[6] [9]
21	Hideyuki Ozaki	[3]
22	Kazunori Saito	[4] [7] [8] [10] [11]
23	Setsuo Wake	[3]
24	Naoya Watanabe	[3]
25	Akira Yamazaki	[3]
26	Tsutomu Yoshihara	[2] [3]