 | 2009 |
|---|
| 10 |       | Shunsuke Okumura,
Yusuke Iguchi,
Shusuke Yoshimoto,
Hidehiro Fujiwara,
Hiroki Noguchi,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme.
ISQED 2009: 659-663 |
| 9 | | Hidehiro Fujiwara,
Shunsuke Okumura,
Yusuke Iguchi,
Hiroki Noguchi,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection.
VLSI Design 2009: 295-300 |
| 8 | | Hidehiro Fujiwara,
Shunsuke Okumura,
Yusuke Iguchi,
Hiroki Noguchi,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A Dependable SRAM with 7T/14T Memory Cells.
IEICE Transactions 92-C(4): 423-432 (2009) |
| 2008 |
|---|
| 7 | | Hidehiro Fujiwara,
Shunsuke Okumura,
Yusuke Iguchi,
Hiroki Noguchi,
Yasuhiro Morita,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
Quality of a Bit (QoB): A New Concept in Dependable SRAM.
ISQED 2008: 98-102 |
| 6 | | Hidehiro Fujiwara,
Koji Nii,
Hiroki Noguchi,
Junichi Miyakoshi,
Yuichiro Murachi,
Yasuhiro Morita,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering.
IEEE Trans. VLSI Syst. 16(6): 620-627 (2008) |
| 5 | | Hiroki Noguchi,
Yusuke Iguchi,
Hidehiro Fujiwara,
Shunsuke Okumura,
Yasuhiro Morita,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.
IEICE Transactions 91-C(4): 543-552 (2008) |
| 2007 |
|---|
| 4 | | Hiroki Noguchi,
Yusuke Iguchi,
Hidehiro Fujiwara,
Yasuhiro Morita,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing.
ISVLSI 2007: 107-112 |
| 3 | | Yasuhiro Morita,
Hidehiro Fujiwara,
Hiroki Noguchi,
Yusuke Iguchi,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme.
IEICE Transactions 90-A(12): 2695-2702 (2007) |
| 2 | | Yasuhiro Morita,
Hidehiro Fujiwara,
Hiroki Noguchi,
Yusuke Iguchi,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes.
IEICE Transactions 90-C(10): 1949-1956 (2007) |
| 2006 |
|---|
| 1 | | Yasuhiro Morita,
Hidehiro Fujiwara,
Hiroki Noguchi,
Kentaro Kawakami,
Junichi Miyakoshi,
Shinji Mikami,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond.
IEICE Transactions 89-A(12): 3634-3641 (2006) |
