| 2009 | ||
|---|---|---|
| 32 | Akira Otsuki, Kenichi Okada: The study of the knowledge optimization tool. GEC Summit 2009: 443-450 | |
| 31 | Hiromitsu Tomozawa, Kiyoshi Oguchi, Hiroshi Shigeno, Kenichi Okada: Message Sending Method Using Patients' Priority for Medical Sensor Network. ICDCS Workshops 2009: 194-200 | |
| 30 | Akira Otsuki, Kenichi Okada: Construction of Optimized Knowledge and New Knowledge Creation Support Tool. KES-AMSTA 2009: 500-513 | |
| 29 | Hirotaka Sugawara, Kenichi Okada, Kazuya Masu: Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit. IEICE Transactions 92-A(2): 401-410 (2009) | |
| 2008 | ||
| 28 | Hong Phuc Ninh, Takashi Moue, Takashi Kurashina, Kenichi Okada, Akira Matsuzawa: A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio. ASP-DAC 2008: 103-104 | |
| 27 | Susumu Sadoshima, Satoshi Fukuda, Tackya Yammouch, Hiroyuki Ito, Kenichi Okada, Kazuya Masu: Small-area CMOS RF distributed mixer using multi-port inductors. ASP-DAC 2008: 105-106 | |
| 26 | Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu: LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process. ASP-DAC 2008: 97-98 | |
| 25 | Shoichi Hara, Takeshi Ito, Kenichi Okada, Akira Matsuzawa: Design space exploration of low-phase-noise LC-VCO using multiple-divide technique. ISCAS 2008: 1966-1969 | |
| 24 | Kazuya Masu, Kenichi Okada: Reconfigurable RF CMOS Circuit for Cognitive Radio. IEICE Transactions 91-B(1): 10-13 (2008) | |
| 23 | Ning Li, Win Chaivipas, Kenichi Okada, Akira Matsuzawa: Analysis of CMOS Transconductance Amplifiers for Sampling Mixers. IEICE Transactions 91-C(6): 871-878 (2008) | |
| 22 | Win Chaivipas, Kenichi Okada, Akira Matsuzawa: Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators. IEICE Transactions 91-C(6): 918-927 (2008) | |
| 2007 | ||
| 21 | Satoshi Fukuda, D. Kawazoe, Kenichi Okada, Kazuya Masu: Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation. ASP-DAC 2007: 104-105 | |
| 20 | Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu: A Multi-Drop Transmission-Line Interconnect in Si LSI. ASP-DAC 2007: 118-119 | |
| 19 | K. Ohashi, Y. Ito, Yoshiaki Yoshihara, Kenichi Okada, Kazuya Masu: A Wideband CMOS LC-VCO Using Variable Inductor. ASP-DAC 2007: 98-99 | |
| 18 | Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu: A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. ISQED 2007: 21-26 | |
| 17 | Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu: Adaptable wire-length distribution with tunable occupation probability. SLIP 2007: 1-8 | |
| 16 | Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Tatsuya Ito, Kazuhisa Itoi, Masakazu Sato, Ryozo Yamauchi, Kazuya Masu: Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology. IEICE Transactions 90-C(3): 641-643 (2007) | |
| 2006 | ||
| 15 | D. Kawazoe, Hirotaka Sugawara, Tatsuya Ito, Kenichi Okada, Kazuya Masu: Reconfigurable CMOS low noise amplifier for self compensation. ISCAS 2006 | |
| 14 | Takumi Uezono, Kenichi Okada, Kazuya Masu: Via Distribution Model for Yield Estimation. ISQED 2006: 479-484 | |
| 13 | Kenichi Okada, Takumi Uezono, Kazuya Masu: Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology. PATMOS 2006: 181-190 | |
| 12 | Takumi Uezono, Kenichi Okada, Kazuya Masu: Statistical Modeling of a Via Distribution for Yield Estimation. IEICE Transactions 89-A(12): 3579-3584 (2006) | |
| 11 | Kazuya Masu, Kenichi Okada, Hiroyuki Ito: RF Passive Components Using Metal Line on Si CMOS. IEICE Transactions 89-C(6): 681-691 (2006) | |
| 2005 | ||
| 10 | Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu: Evaluation of on-chip transmission line interconnect using wire length distribution. ASP-DAC 2005: 133-138 | |
| 9 | Kenichi Okada, Yoshiaki Yoshihara, Hirotaka Sugawara, Kazuya Masu: A dynamic reconfigurable RF circuit architecture. ASP-DAC 2005: 683-686 | |
| 8 | Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu: Wire Length Distribution Model Considering Core Utilization for System on Chip. ISVLSI 2005: 276-277 | |
| 7 | Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu: Prediction of delay time for future LSI using on-chip transmission line interconnects. SLIP 2005: 7-12 | |
| 6 | Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu: Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model. IEICE Transactions 88-A(12): 3358-3366 (2005) | |
| 5 | Hidenari Nakashima, Naohiro Takagi, Junpei Inoue, Kenichi Okada, Kazuya Masu: Evaluation of X Architecture Using Interconnect Length Distribution. IEICE Transactions 88-A(12): 3437-3444 (2005) | |
| 4 | Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu: Wire Length Distribution Model for System LSI. IEICE Transactions 88-A(12): 3445-3452 (2005) | |
| 3 | Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu: Wide Tuning Range LC-VCO Using Variable Inductor for Reconfigurable RF Circuit. IEICE Transactions 88-A(2): 507-512 (2005) | |
| 2004 | ||
| 2 | Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu: ULSI Interconnect Length Distribution Model Considering Core Utilization. DATE 2004: 1210-1217 | |
| 1 | Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu: Inductance-Tuned LC-VCO for Reconfigurable RF Circuit Design. IEICE Electronic Express 1(7): 156-159 (2004) | |