| 2008 | ||
|---|---|---|
| 57 | Vijaykrishnan Narayanan, C. P. Ravikumar, Jörg Henkel, Ali Keshavarzi, Vojin G. Oklobdzija, Barry M. Pangrle: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008 ACM 2008 | |
| 56 | Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija: Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements. PATMOS 2008: 268-276 | |
| 55 | Vojin G. Oklobdzija: Reduced Instruction Set Computing. Wiley Encyclopedia of Computer Science and Engineering 2008 | |
| 2007 | ||
| 54 | Mandeep Singh, Christophe Giacomotto, Bart R. Zeydel, Vojin G. Oklobdzija: Logic Style Comparison for Ultra Low Power Operation in 65nm Technology. PATMOS 2007: 181-190 | |
| 2006 | ||
| 53 | Bart R. Zeydel, Vojin G. Oklobdzija: Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations. PATMOS 2006: 127-136 | |
| 52 | Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija: Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design. PATMOS 2006: 148-156 | |
| 51 | Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija: Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations. PATMOS 2006: 360-369 | |
| 50 | Xiao Yan Yu, Robert K. Montoye, Kevin J. Nowka, Bart R. Zeydel, Vojin G. Oklobdzija: Circuit Design Style for Energy Efficiency: LSDL and Compound Domino. PATMOS 2006: 47-55 | |
| 49 | Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija: Energy optimization of pipelined digital systems using circuit sizing and supply scaling. IEEE Trans. VLSI Syst. 14(2): 122-134 (2006) | |
| 2005 | ||
| 48 | Vojin G. Oklobdzija: Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, Marina del Rey, CA, USA, October 24-26, 2005 IASTED/ACTA Press 2005 | |
| 47 | Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija: Architectural Considerations for Energy Efficiency. ICCD 2005: 13-16 | |
| 46 | Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija: Low- and Ultra Low-Power Arithmetic Units: Design and Comparison. ICCD 2005: 249-252 | |
| 45 | Bart R. Zeydel, Theo T. J. H. Kluter, Vojin G. Oklobdzija: Efficient Mapping of Addition Recurrence Algorithms in CMOS. IEEE Symposium on Computer Arithmetic 2005: 107-113 | |
| 44 | Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija: A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. PATMOS 2005: 724-732 | |
| 43 | Nikola Nedovic, Vojin G. Oklobdzija: Dual-edge triggered storage elements and clocking strategy for low-power systems. IEEE Trans. VLSI Syst. 13(5): 577-590 (2005) | |
| 42 | Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy: Comparison of high-performance VLSI adders in the energy-delay space. IEEE Trans. VLSI Syst. 13(6): 754-758 (2005) | |
| 2003 | ||
| 41 | Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy: Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders. IEEE Symposium on Computer Arithmetic 2003: 272-279 | |
| 40 | Vojin G. Oklobdzija, Ram Krishnamurthy: Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs. IEEE Symposium on Computer Arithmetic 2003: 280 | |
| 39 | Aamir A. Farooqui, Vojin G. Oklobdzija, Sadiq M. Sait: Area-time optimal adder with relative placement generator. ISCAS (5) 2003: 141-144 | |
| 38 | Xiao Yan Yu, Vojin G. Oklobdzija, William W. Walker: An efficient transistor optimizer for custom circuits. ISCAS (5) 2003: 197-200 | |
| 37 | Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija: Energy Optimization of High-Performance Circuits. PATMOS 2003: 399-408 | |
| 36 | Vojin G. Oklobdzija: Clocking and clocked storage elements in a multi-gigahertz environment. IBM Journal of Research and Development 47(5-6): 567-584 (2003) | |
| 2002 | ||
| 35 | Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija: Comparative analysis of double-edge versus single-edge triggered clocked storage elements. ISCAS (5) 2002: 105-108 | |
| 34 | Vojin G. Oklobdzija, Jens Sparsø: Future directions in clocking multi-ghz systems. ISLPED 2002: 219 | |
| 33 | Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija: Conditional pre-charge techniques for power-efficient dual-edge clocking. ISLPED 2002: 56-59 | |
| 32 | Martin Saint-Laurent, Vojin G. Oklobdzija, Simon S. Singh, Madhavan Swaminathan: Optimal Sequencing Energy Allocation for CMOS Integrated Systems. ISQED 2002: 194-199 | |
| 31 | Vojin G. Oklobdzija: Clocking and Clocked Storage Elements in Multi-GHz Environment. PATMOS 2002: 128-145 | |
| 30 | Hoang Q. Dao, Vojin G. Oklobdzija: Performance Comparison of VLSI Adders Using Logical Effort. PATMOS 2002: 25-34 | |
| 2001 | ||
| 29 | Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija: Timing Characterization of Dual-edge Triggered Flip-flops. ICCD 2001: 538-541 | |
| 28 | Hoang Q. Dao, Kevin J. Nowka, Vojin G. Oklobdzija: Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation. ISLPED 2001: 56-59 | |
| 2000 | ||
| 27 | Nikola Nedovic, Vojin G. Oklobdzija: Dynamic Flip-Flop with Improved Power. ICCD 2000: 323- | |
| 26 | Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current: Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. IEEE Trans. VLSI Syst. 8(4): 460-463 (2000) | |
| 1999 | ||
| 25 | Aamir A. Farooqui, Vojin G. Oklobdzija: VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing. Great Lakes Symposium on VLSI 1999: 30-33 | |
| 1998 | ||
| 24 | Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa: A unified approach in the analysis of latches and flip-flops for low-power systems. ISLPED 1998: 227-232 | |
| 23 | Paul F. Stelling, Charles U. Martel, Vojin G. Oklobdzija, R. Ravi: Optimal Circuits for Parallel Multipliers. IEEE Trans. Computers 47(3): 273-285 (1998) | |
| 1997 | ||
| 22 | Paul F. Stelling, Vojin G. Oklobdzija: Implementing Multiply-Accumulate Operation in Multiplication Time. IEEE Symposium on Computer Arithmetic 1997: 99- | |
| 21 | Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current: Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results. ISLPED 1997: 323-327 | |
| 1996 | ||
| 20 | K. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic: Low-Energy Logic Circuit Techniques for Multiple-Valued Logic. ISMVL 1996: 86- | |
| 19 | Vojin G. Oklobdzija, David Villeger, Simon S. Liu: A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach. IEEE Trans. Computers 45(3): 294-306 (1996) | |
| 18 | Vojin G. Oklobdzija, Belle Wei: Guest editors' introduction. VLSI Signal Processing 14(3): 239-240 (1996) | |
| 17 | Richard H. Strandberg, Luis G. Bustamante, Vojin G. Oklobdzija, Michael A. Soderstrand, Jean-Claude Duc: Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters. VLSI Signal Processing 14(3): 303-309 (1996) | |
| 16 | Paul F. Stelling, Vojin G. Oklobdzija: Design strategies for optimal hybrid final adders in a parallel multiplier. VLSI Signal Processing 14(3): 321-331 (1996) | |
| 1995 | ||
| 15 | Charles U. Martel, Vojin G. Oklobdzija, R. Ravi, Paul F. Stelling: Design Strategies for Optimal Multiplier Circuits. IEEE Symposium on Computer Arithmetic 1995: 42-49 | |
| 14 | K. J. Runge, L. P. Lee, J. Correa, R. T. Scalettar, Vojin G. Oklobdzija: Monte Carlo and molecular dynamics simulations using p4. IPPS 1995: 53-59 | |
| 13 | Vojin G. Oklobdzija, David Villeger: Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology. IEEE Trans. VLSI Syst. 3(2): 292-301 (1995) | |
| 12 | R. T. Scalettar, K. J. Runge, J. Correa, P. Lee, Vojin G. Oklobdzija, J. L. Vujic: Simulations of Interacting Many Body Systems Using P4. International Journal of High Speed Computing 7(3): 327-349 (1995) | |
| 11 | Mikhail N. Dorojevets, Vojin G. Oklobdzija: Multithreaded Decoupled Architecture. International Journal of High Speed Computing 7(3): 465-480 (1995) | |
| 1994 | ||
| 10 | Vojin G. Oklobdzija: High-Performance Computer Arithmetic and Implementations: Introduction. HICSS (1) 1994: 280-281 | |
| 9 | Rupinder Hundal, Vojin G. Oklobdzija: Determination of Optimal Sizes for a First and Second Level SRAM-DRAM On-Chip Cache Combination. ICCD 1994: 60-64 | |
| 8 | Vojin G. Oklobdzija: An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis. IEEE Trans. VLSI Syst. 2(1): 124-128 (1994) | |
| 7 | Vojin G. Oklobdzija, David Villeger, Thierry Soulas: An integrated multiplier for complex numbers. VLSI Signal Processing 7(3): 213-222 (1994) | |
| 1992 | ||
| 6 | Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija: Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. IEEE Trans. Computers 41(8): 920-930 (1992) | |
| 1991 | ||
| 5 | Vojin G. Oklobdzija, Belle Wei: Introduction. VLSI Signal Processing 3(4): 263 (1991) | |
| 4 | Brian D. Lee, Vojin G. Oklobdzija: Improved CLA scheme with optimized delay. VLSI Signal Processing 3(4): 265-274 (1991) | |
| 1988 | ||
| 3 | Vojin G. Oklobdzija, Earl R. Barnes: On Implementing Addition in VLSI Technology. J. Parallel Distrib. Comput. 5(6): 716-728 (1988) | |
| 1984 | ||
| 2 | J. Paul Roth, Vojin G. Oklobdzija, John F. Beetem: Test Generation for FET Switching Circuits. ITC 1984: 59-62 | |
| 1982 | ||
| 1 | Vojin G. Oklobdzija, Milos D. Ercegovac: A On-Line Square Root Algorithm. IEEE Trans. Computers 31(1): 70-75 (1982) | |