 | 2009 |
|---|
| 5 |       | Shunsuke Okumura,
Yusuke Iguchi,
Shusuke Yoshimoto,
Hidehiro Fujiwara,
Hiroki Noguchi,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme.
ISQED 2009: 659-663 |
| 4 | | Hidehiro Fujiwara,
Shunsuke Okumura,
Yusuke Iguchi,
Hiroki Noguchi,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection.
VLSI Design 2009: 295-300 |
| 3 | | Hidehiro Fujiwara,
Shunsuke Okumura,
Yusuke Iguchi,
Hiroki Noguchi,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A Dependable SRAM with 7T/14T Memory Cells.
IEICE Transactions 92-C(4): 423-432 (2009) |
| 2008 |
|---|
| 2 | | Hidehiro Fujiwara,
Shunsuke Okumura,
Yusuke Iguchi,
Hiroki Noguchi,
Yasuhiro Morita,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
Quality of a Bit (QoB): A New Concept in Dependable SRAM.
ISQED 2008: 98-102 |
| 1 | | Hiroki Noguchi,
Yusuke Iguchi,
Hidehiro Fujiwara,
Shunsuke Okumura,
Yasuhiro Morita,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.
IEICE Transactions 91-C(4): 543-552 (2008) |
