| 2009 | ||
|---|---|---|
| 5 | Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet: High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving. IEICE Transactions 92-C(6): 867-874 (2009) | |
| 2008 | ||
| 4 | Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu: High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. ISMVL 2008: 70-75 | |
| 3 | Kazuyasu Mizusawa, Naoya Onizawa, Takahiro Hanyu: Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling. IEICE Transactions 91-C(4): 581-588 (2008) | |
| 2006 | ||
| 2 | Naoya Onizawa, Takahiro Hanyu: Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic. IEICE Transactions 89-C(11): 1575-1580 (2006) | |
| 2005 | ||
| 1 | Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu: Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders. ISMVL 2005: 138-143 | |
| 1 | Vincent C. Gaudet | [5] |
| 2 | Takahiro Hanyu | [1] [2] [3] [4] [5] |
| 3 | Kazuyasu Mizusawa | [3] |
| 4 | Akira Mochizuki | [1] |
| 5 | Tasuku Nagai | [4] |