 | 2009 |
|---|
| 8 |       | Takaaki Okumura,
Atsushi Kurokawa,
Hiroo Masuda,
Toshiki Kanamoto,
Masanori Hashimoto,
Hiroshi Takafuji,
Hidenari Nakashima,
Nobuto Ono,
Tsuyoshi Sakata,
Takashi Sato:
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations.
IEICE Transactions 92-A(4): 990-997 (2009) |
| 2007 |
|---|
| 7 | | Hiroyuki Kobayashi,
Nobuto Ono,
Takashi Sato,
Jiro Iwai,
Hidenari Nakashima,
Takaaki Okumura,
Masanori Hashimoto:
Proposal of Metrics for SSTA Accuracy Evaluation.
IEICE Transactions 90-A(4): 808-814 (2007) |
| 2006 |
|---|
| 6 | | Takashi Nojima,
Nobuto Ono,
Shigetoshi Nakatake,
Toru Fujimura,
Koji Okazaki,
Yoji Kajitani:
Adaptive Porting of Analog IPs with Reusable Conservative Properties.
ISVLSI 2006: 18-23 |
| 5 | | Takashi Sato,
Junji Ichimiya,
Nobuto Ono,
Masanori Hashimoto:
On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature.
IEICE Transactions 89-A(12): 3491-3499 (2006) |
| 2005 |
|---|
| 4 | | Takashi Sato,
Junji Ichimiya,
Nobuto Ono,
Koutaro Hachiya,
Masanori Hashimoto:
On-chip thermal gradient analysis and temperature flattening for SoC design.
ASP-DAC 2005: 1074-1077 |
| 3 | | Atsushi Kurokawa,
Masaharu Yamamoto,
Nobuto Ono,
Tetsuro Kage,
Yasuaki Inoue,
Hiroo Masuda:
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.
ISQED 2005: 153-158 |
| 2 | | Takashi Sato,
Junji Ichimiya,
Nobuto Ono,
Koutaro Hachiya,
Masanori Hashimoto:
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design.
IEICE Transactions 88-A(12): 3382-3389 (2005) |
| 2004 |
|---|
| 1 | | Atsushi Kurokawa,
Nobuto Ono,
Tetsuro Kage,
Hiroo Masuda:
DEPOGIT: dense power-ground interconnect architecture for physical design integrity.
ASP-DAC 2004: 517-522 |
