Chia Yee Ooi

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2008

5 Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi: A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1535-1544 (2008)

2007

4 Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara: Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tau^k-Notation. IEICE Transactions 90-D(8): 1202-1212 (2007)

2006

3 Chia Yee Ooi, Hideo Fujiwara: A New Class of Sequential Circuits with Acyclic Test Generation Complexity. ICCD 2006

2005

2 Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara: Classification of Sequential Circuits Based on tau^k Notation and Its Applications. IEICE Transactions 88-D(12): 2738-2747 (2005)

2004

1 Chia Yee Ooi, Hideo Fujiwara: Classification of Sequential Circuits Based on ?k Notation. Asian Test Symposium 2004: 348-353

	2008
5		Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi: A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1535-1544 (2008)
	2007
4		Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara: Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tau^k-Notation. IEICE Transactions 90-D(8): 1202-1212 (2007)
	2006
3		Chia Yee Ooi, Hideo Fujiwara: A New Class of Sequential Circuits with Acyclic Test Generation Complexity. ICCD 2006
	2005
2		Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara: Classification of Sequential Circuits Based on tau^k Notation and Its Applications. IEICE Transactions 88-D(12): 2738-2747 (2005)
	2004
1		Chia Yee Ooi, Hideo Fujiwara: Classification of Sequential Circuits Based on ?k Notation. Asian Test Symposium 2004: 348-353

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