 | 2007 |
|---|
| 14 |       | Guoji Zhu,
Ajoy Opal:
Per-Element Decompostion in Distortion Analysis.
ISCAS 2007: 449-452 |
| 2006 |
|---|
| 13 | | Guoji Zhu,
Ajoy Opal:
Sensitivity analysis of nonlinear circuits using Volterra series.
ISCAS 2006 |
| 2004 |
|---|
| 12 |  | Bendong Sun,
Fei Yuan,
Ajoy Opal:
Inductive peaking in wideband CMOS current amplifiers.
ISCAS (4) 2004: 285-288 |
| 2002 |
|---|
| 11 | | Fei Yuan,
Ajoy Opal:
An efficient transient analysis algorithm for mildly nonlinearcircuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(6): 662-673 (2002) |
| 2001 |
|---|
| 10 | | Y. Dong,
Ajoy Opal:
An overview on computer-aided analysis techniques for sigma-delta modulators.
ISCAS (5) 2001: 423-426 |
| 2000 |
|---|
| 9 | | Jennifer Y. Dong,
Ajoy Opal:
Time-domain thermal noise simulation of switched capacitor circuitsand delta-sigma modulators.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 473-481 (2000) |
| 1999 |
|---|
| 8 | | Fei Yuan,
Ajoy Opal:
Sensitivity analysis of periodically switched linear circuits using an adjoint network technique.
ISCAS (5) 1999: 331-334 |
| 7 | | Fei Yuan,
Ajoy Opal:
Distortion analysis of periodically switched nonlinear circuits.
ISCAS (5) 1999: 499-502 |
| 1997 |
|---|
| 6 | | Ajoy Opal:
The transition matrix for linear circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 427-436 (1997) |
| 1996 |
|---|
| 5 | | Ajoy Opal:
Sampled data simulation of linear and nonlinear circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(3): 295-307 (1996) |
| 1995 |
|---|
| 4 | | Ajoy Opal,
Kaamran Raahemifar:
Zero State Response of Linear Circuits to Exponential Inputs.
ISCAS 1995: 1484-1487 |
| 1993 |
|---|
| 3 | | Ajoy Opal:
Group Delay Analysis of Switched Circuits.
ISCAS 1993: 1022-1025 |
| 2 | | Jiri Vlach,
Ajoy Opal,
Jacek Wojciechowski:
Simulation of Networks with Inconsistent Initial Conditions.
ISCAS 1993: 1627-1630 |
| 1991 |
|---|
| 1 | | Genhong Ruan,
Jiri Vlach,
James A. Barby,
Ajoy Opal:
Analog functional simulator for multilevel systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 565-576 (1991) |
